module test;
reg [14*8:1] str_v;
initial
begin
str_v="hello";
$display ("%s is stored as %h",str_v,str_v);
str_v={str_v,"!!!"};
$display ("%s is stored as %h",str_v,str_v);
end
endmodule
After enterin...
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introduction
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Created on: 2012-9-8
Author: zhang bin
Study Notes
for msp430g2553
redesigned by zhang bin
2012-09-08
versions : 12_09_01
All Rights Reserved
...[Details]
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Connect the assembly test program:
B_COM0SS:; Comparator CM0:
CLR CM0M; Clear CM0M register.; Reset comparator CM0.;
Set the function mode of comparator CM0.;
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#include reg51.h
void delay(int);
void main()
{
int i;
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FPGA/CPLD
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