MO8256
0.3 ps Jitter Oscillator for Networking
Features
156.250000 MHz, 156.253906 MHz, 156.257800 MHz,
156.257812 MHz, 156.261718 MHz for Ethernet applications
100% pin-to-pin drop-in replacement to quartz-based oscillators
Ultra-low phase jitter: 0.3 ps
Frequency stability as low as ±10 PPM
Industrial or extended commercial temperature range
LVCMOS/LVTTL compatible output
Standby or output enable modes
Standard 4-pin packages: 2.7 x 2.4 (compatible with 2.5 x 2.0 footprint),
3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mm x mm
Outstanding silicon reliability of 2 FIT or 500 million hour MTBF
Pb-free, RoHS and REACH compliant
Ultra-short lead time
Applications
SATA,
SAS, Ethernet, 10Gb Ethernet, XAUI
storage, networking, telecom, industrial control
Computing,
Electrical Characteristics
Parameter
Output Frequency Range
Symbol
f
Min.
Typ.
Max.
156.250000, 156.253906
156.257800, 156.257812
156.261718
-10
–
+10
-20
-25
-50
Operating Temperature Range
T_use
-20
-40
+1.71
Supply Voltage
Vdd
+2.25
+2.52
+2.97
Current Consumption
Idd
–
–
–
–
–
Standby Current
Duty Cycle
Rise/Fall Time
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Startup Time
OE Enable/Disable Time
Resume Time
I_std
–
DC
Tr, Tf
VOH
VOL
VIH
VIL
Z_in
T_start
T_oe
T_resume
45
–
–
–
90%
–
70%
–
–
2.0
–
–
–
–
–
–
-1.5
-5.0
–
–
1.2
2.2
3.4
–
–
–
–
100
–
7.0
–
6.0
1.5
2.0
0.25
–
–
+10
55
2.0
–
–
–
10%
–
30%
250
–
10
150
10
2.0
3.0
0.3
+1.5
+5.0
μA
%
ns
ns
ns
Vdd
Vdd
Vdd
Vdd
kΩ
MΩ
ms
ns
ms
ps
ps
ps
PPM
PPM
In standby mode, measured from the time
ST
pin crosses 50%
threshold. Refer to
Figure 5.
Vdd = +2.5V, +2.8V or +3.3V
Vdd = +1.8V
IEEE802.3-2005 10GbE jitter measurement specifications
+25 °C
+25 °C
15 pF load, 10% - 90% Vdd
30 pF load, 10% - 90% Vdd
45 pF load, 10% - 90% Vdd
IOH = -6.0 mA, IOL = +6.0 mA, (Vdd = +3.3V, +2.8V, +2.5V)
IOH = -3.0 mA, IOL = +3.0 mA, (Vdd = +1.8V)
Pin 1, OE or
ST
Pin 1, OE or
ST
Pin 1, OE logic high or logic low, or
ST
logic high
Pin 1,
ST
logic low
Measured from the time Vdd reaches its rated minimum value
–
–
–
–
–
+1.8
+2.5
+2.8
+3.3
+31
+29
–
–
–
+20
+25
+50
+70
+85
+1.89
+2.75
+3.08
+3.63
+33
+31
+31
+30
+70
Unit
MHz
PPM
PPM
PPM
PPM
°C
°C
V
V
V
V
mA
mA
mA
mA
μA
No load condition, Vdd = +2.5V, +2.8V or +3.3V
No load condition, Vdd = +1.8V
Vdd = +2.5V, +2.8V or +3.3V, OE = GND, output is Weakly
Pulled Down
Vdd = +1.8 V. OE = GND, output is Weakly Pulled Down
Vdd = +2.5V, +2.8V or +3.3V,
ST
= GND, output is Weakly
Pulled Down
Vdd = +1.8 V.
ST
= GND, output is Weakly Pulled Down
Supply voltages between +2.5V and +3.3V can be supported.
Contact KDS for additional information.
Extended Commercial
Industrial
Inclusive of Initial tolerance at +25 °C, and variations over
operating temperature, rated power supply voltage and load
Condition
Frequency Stability
F_stab
OE Disable Current
I_OD
RMS Period Jitter
RMS Phase Jitter (random)
First year Aging
10-year Aging
T_jitt
T_phj
F_aging
Note:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. Contact KDS for custom drive strength to drive higher or multiple load, or SoftEdge™ option for EMI reduction.
Daishinku Corp.
Rev. 1.11
1389 Shinzaike, Hiraoka-cho, Kakogawa, Hyogo 675-0194 Japan
+81-79-426-3211
www.kds.info
Revised March 4, 2013
MO8256
0.3 ps Jitter Oscillator for Networking
Pin Configuration
Pin
Symbol
Output
Enable
1
OE/ ST
Standby
2
3
4
Notes:
3. A pull-up resistor of <10 kΩ between OE/ ST pin and Vdd is recommended in high noise environment.
GND
OUT
VDD
Power
Output
Power
[3]
Functionality
H or Open : specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open
[3]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
Electrical ground
Oscillator output
Power supply voltage
GND
2
Top View
OE/ST
1
4
VDD
3
OUT
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual
performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
–
–
Max.
+150
+4.0
+2000
+260
Unit
°C
V
V
°C
Thermal Consideration
Package
7050
5032
3225
2520
JA, 4 Layer Board
(°C/W)
191
97
109
117
JA, 2 Layer Board
(°C/W)
263
199
212
222
JC, Bottom
(°C/W)
30
24
27
26
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.11
Page 2 of 5
www.kds.info
MO8256
0.3 ps Jitter Oscillator for Networking
Test Circuit and Waveform
Vdd
Vout
Test
Point
tr
4
Power
Supply
0.1µF
1
2
3
tf
90% Vdd
15pF
(including probe
and fixture
capacitance)
50%
10% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
OE/ST Function
Vdd
1kΩ
Figure 1. Test Circuit
Figure 2. Waveform
Notes:
4. Duty Cycle is computed as Duty Cycle = TH/Period.
5. MO8256 supports the configurable duty cycle feature. For custom duty cycle at any given frequency, contact KDS.
Timing Diagram
90% Vdd, 2.5/2,8/3.3V devices
Vdd
95% Vdd, 1.8V devices
Vdd
Pin 4 Voltage
NO Glitch first cycle
T_start
CLK Output
50% Vdd
T_resume
ST Voltage
CLK Output
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 3. Startup Timing (OE/ST Mode)
Vdd
50% Vdd
T_OE
CLK Output
Figure 4. Standby Resume Timing (ST Mode Only)
Vdd
OE Voltage
OE Voltage
50% Vdd
CLK Output
T_OE
HZ
T_OE: Time to re-enable the clock output
T_OE: Time to put the output drive in High Z mode
Figure 5. OE Enable Timing (OE Mode Only)
Figure 6. OE Disable Timing (OE Mode Only)
Notes:
6. MO8256 supports “no runt” pulses and “no glitch” output during startup or resume.
7. MO8256 supports gated output which is accurate within rated frequency stability from the first cycle.
Rev. 1.11
Page 3 of 5
www.kds.info
Analog electronics
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