FQV2111L7.5PFI datasheet, PDF - EEWORLD Datasheet

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FQV2111L7.5PFI: DescriptionFIFO, 512KX9, 5ns, Synchronous, CMOS, PQFP64; Categorystorage storage; File Size355KB，33 Pages; ManufacturerAMICC [AMIC TECHNOLOGY]

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FQV2111L7.5PFI Overview

FIFO, 512KX9, 5ns, Synchronous, CMOS, PQFP64

FQV2111L7.5PFI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	QFP, QFP64,.6SQ,32
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	5 ns
Maximum clock frequency (fCLK)	133 MHz
JESD-30 code	S-PQFP-G64
memory density	4718592 bi
Memory IC Type	OTHER FIFO
memory width	9
Number of terminals	64
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX9
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP64,.6SQ,32
Package shape	SQUARE
Package form	FLATPACK
power supply	3.3 V
Certification status	Not Qualified
Maximum standby current	0.02 A
Maximum slew rate	0.055 mA
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Base Number Matches	1

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FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261

FlexQ II

3.3 Volt Synchronous x9 First-In/First-Out Queue

Memory Configuration

524,288 x 9

262,144 x 9

131,072 x 9

65,536 x 9

32,768 x 9

16,384 x 9

Part Number

FQV2111

FQV2101

FQV291

FQV281

FQV271

FQV261

Key Features

•

Industry leading First-In/First-Out Queues (up to 133MHz)

Write cycle time of 7.5ns independent of Read cycle time

Read cycle time of 7.5ns independent of Write cycle time

User selectable input and output port bus-sizing

Big Endian/Little Endian user selectable byte representation

3.3V power supply

5V input tolerant on all control and data input pins

5V output tolerant on all flags and data output pins

Master Reset clears all previously programmed configurations including Write and Read pointers.

Partial Reset clears Write and Read pointers but maintains all previously programmed configurations.

First Word Fall Through (FWFT) and Standard Timing modes

Preset for Almost Full ( PRAF ) and Almost Empty ( PRAE ) offsets values

Parallel/Serial programming of PRAF and PRAE offset values

Full, Empty, Almost Full, Almost Empty and Half Full indicators

Asynchronous output enable tri-state data output drivers

Data retransmission

Available package: 64 - pin Plastic Thin Quad Flat Pack (TQFP), 64 – pin Slim Thin Quad Flat Pack (STQFP)

(0°C to 70°C) Commercial operating temperature available for cycle time of 7.5ns and above

(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above

Product Description

HBA’s FlexQ™ II offers industry leading FIFO queuing bandwidth (up to 1.5 Gbps) with a wide range of memory

configurations (from 16,384 x 9 to

524,288

x 9). System designer has full flexibility of implementing deeper and wider queues

using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between

transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation

of virtual queue depths.

5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous

Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching

capability.

Master Reset clears all previously programmed configurations by providing a low pulse on

MRST

pin. In addition, Write and

Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will

initialize Write and Read pointers to zero.

In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high

transition of RCLK. Subsequent reads from the queue will require asserting

REN

. This feature is useful when implementing

depth expansion functions. In this mode,

DRDY

and QRDY are used instead of

FULL

and

EMPTY

respectively.

In Standard mode, always assert

REN

for read operation.

FULL

and

EMPTY

are used instead of

DRDY

and QRDY

respectively.

3F209C

OCTOBER 2002

Page 1 of 1

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