Freescale Semiconductor
Technical Data
Document Number: MC33689
Rev. 7.0, 8/2006
System Basis Chip with LIN
Transceiver
The 33689 is a SPI-controlled System Basis Chip (SBC) that
combines many frequently used functions in an MCU-based system
plus a Local Interconnect Network (LIN) transceiver. Applications
include power window, mirror, and seat controls. The 33689 has a
5.0 V, 50 mA low dropout regulator with full protection and reporting
features. The device provide full SPI-readable diagnostics and a
selectable timing watchdog for detecting errant operation.
The LIN transceiver waveshaping circuitry can be disabled for
higher data rates. One 50 mA and two 150 mA high-side switches with
output protection are available to drive inductive or resistive loads. The
150 mA switches can be pulse-width modulated (PWM).
Two high-voltage inputs are available for contact monitoring or as
external wake-up inputs. A current sense operational amplifier is
available for load current monitoring.
The 33689 has three operational modes:
• Normal (all functions available)
• Sleep (VDD OFF, wake-up via LIN bus or wake-up inputs)
• Stop (VDD ON, wake-up via MCU, LIN bus, or wake-up inputs)
Features
•
•
•
•
•
•
•
Full-Duplex SPI Interface at Frequencies up to 4.0 MHz
LIN Transceiver Capable to 100 kbps with Waveshaping Capability
5.0 V Low Dropout Regulator Full Fault Detection and Protection
One 50 mA and Two 150 mA Protected High-Side Switches
Current Sense Operational Amplifier
The 33689 is compatible with LIN 2.0 Specification Package.
Pb-Free Packaging Designated by Suffix Code EW
VDD VPWR
33689D
SYSTEM BASIS CHIP WITH LIN
DWB SUFFIX
EW SUFFIX (PB-FREE)
98ARH99137A
32-PIN SOICW
ORDERING INFORMATION
Device
MC33689DDWB/R2
MCZ33689DEW/R2
-40°C to 125°C
32 SOICW
Temperature
Range (T
A
)
Package
33689
VS1
VS2
VCC
VDD
WDC
HS3
L1
L2
5.0 V
HS1
CS
SCK
MCU
MOSI
MISO
SPI
CS
SCLK
MOSI
MISO
INT
RST
IN
OUT
TXD
RXD
HS2
E+
E-
GND
TGND
AGND
LIN
BUS
Figure 1. 33689 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VS1
5.0 V/50 mA
Voltage
Regulator
Reset
Control
VDD
RST
VS2
Window
Watchdog
WDC
IN
MOSI
HS1
HS2
Pre-Driver
HS3
SPI
and
Mode
Control
MISO
SCLK
CS
INT
VCC
L1
Current
Sense
Op Amp
E-
E+
OUT
TXD
RXD
L2
VS1
LIN
LIN Physical Interface
GND
TGND
AGND
Figure 2. 33689 Simplified Internal Block Diagram
33689
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
NC
L1
NC
L2
HS3
HS2
HS1
TGND
TGND
VS2
LIN
GND
VS1
NC
VDD
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TXD
RXD
INT
CS
MISO
MOSI
SCLK
TGND
TGND
IN
RST
WDC
E+
E
-
OUT
VCC
Figure 3. 33689 32-SOICW Pin Connections
Table 1. 33689 32-SOICW Pin Definitions
A functional description of each pin can be found in the
Functional Pin Description
section beginning on page
19.
Pin
1, 3, 14
2, 4
5–7
8, 9, 24, 25
10
11
12
13
15
16
17
18
19
20
21
Pin Name
NC
L1, L2
HS3 – HS1
TGND
VS2
LIN
GND
VS1
VDD
AGND
VCC
OUT
E
-
E+
WDC
Formal Name
No Connect
Level Inputs 1 and 2
High-Side Driver
Outputs 3 through 1
Thermal Ground
Voltage Supply 2
LIN Bus
Ground
Voltage Supply 1
5.0 V Regulator
Output
Analog Ground
Power Supply In
Amplifier Output
Amplifier Inverted
Input
Amplifier Non-Inverted
Input
Watchdog
Configuration
(Active Low)
Pin Function
N/A
Input
Output
N/A
Input
Input / Output
N/A
Input
Output
N/A
Input
Output
Input
Input
Reference
Definition
No internal connection to these pins.
Inputs from external switches or from logic circuitry.
High-side (HS) drive power outputs. SPI-controlled for driving system
loads.
Thermal ground pins for the device.
Supply pin for the high-side switches HS1, HS2, and HS3.
Bidirectional pin that represents the single-wire bus transmitter and
receiver.
Electrical ground pin for the device.
Supply pin for the 5.0 V regulator, the LIN physical interface, and the
internal logic.
Output of the 5.0 V regulator.
Analog ground pin for voltage regulator and current sense operational
amplifier.
5.0 V supply for the internal current sense operational amplifier.
Output of the internal current sense operational amplifier.
Inverted input of the internal current sense operational amplifier.
Non-inverted input of the internal current sense operational amplifier.
Configuration pin for the watchdog timer.
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33689 32-SOICW Pin Definitions (continued)
A functional description of each pin can be found in the
Functional Pin Description
section beginning on page
19.
Pin
22
23
26
27
28
29
30
31
32
Pin Name
RST
Formal Name
Reset Output
(Active LOW)
PWM Input Control
Serial Data Clock
Master Out Slave In
Master In Slave Out
Chip Select
(Active LOW)
Interrupt Output
(Active LOW)
Receiver Output
Transmitter Input
Pin Function
Output
Input
Input
Input
Output
Input
Output
Output
Input
Definition
5.0 V regulator and watchdog reset output pin.
External input PWM control pin for high-side switches HS1 and HS2.
Clock input for the SPI of the 33689.
SPI data received by the 33689.
SPI data sent to the MCU by the 33689. When
CS
is HIGH, pin is in the
high-impedance state.
SPI control chip select input pin.
This output pin reports faults to the MCU when an enabled interrupt
condition occurs.
Receiver output of the LIN interface and reports the state of the bus
voltage.
Transmitter input of the LIN interface and controls the state of the bus
output.
IN
SCLK
MOSI
MISO
CS
INT
RXD
TXD
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
ELECTRICAL RATINGS
V
PWR
Supply Voltage at VS1 and VS2
Continuous
Transient (Load Dump)
Supply Voltage at VDD and VCC
Output Current at VDD
Logic Input Voltage at MOSI, SCLK,
CS
, IN, and TXD
Logic Output Voltage at MISO,
INT
,
RST
, and RXD
Input Voltage at E+ and E
-
Input Current at E+ and E
-
Output Voltage at OUT
Output Current at OUT
Input Voltage at L1 and L2
DC Input with a 33 kΩ Resistor
Transient Input with External Component (per ISO7637 Specification) (See
Figure 4,
page
6)
Input / Output Voltage at LIN
DC Voltage
Transient Input Voltage with specified External Component (per ISO7637
Specification) (See
Figure 4,
page
6)
DC Output Voltage at HS1 and HS2
Positive
Negative
DC Output Voltage at HS3
ESD Voltage, Human Body Model
(1)
GND Configured as Ground. TGND and AGND Configured as I/O Pins
LIN, L1, and L2
All Other Pins
ESD Voltage, Charge Device Model
(1)
Corner Pins (Pins 1, 16, 17, and 32)
All other Pins (Pins 2 – 15 and 18 – 31)
V
ESD2
± 750
± 500
± 4000
± 2000
V
V
HS+
V
HS
-
V
HS3
V
ESD1
V
VS2
+ 0.3
Internally Clamped
- 0.3 to V
VS2
+ 0.3
V
V
V
BUSDC
V
BUSTR
-18 to 40
-150 to 100
V
V
LXDC
V
LXTR
-18 to 40
±100
V
V
SUPDC
V
SUPTR
V
DD
I
DD
V
INLOG
V
OUTLOG
V
E+
/ V
E
-
I
E+
/ I
E
-
V
OUT
I
OUT
- 0.3 to 27
40
- 0.3 to 5.5
Internally Limited
- 0.3 to V
DD
+ 0.3
- 0.3 to V
DD
+ 0.3
- 0.3 to 7.0
± 20
- 0.3 to V
CC
+ 0.33
± 20
V
A
V
V
V
mA
V
mA
V
V
Symbol
Value
Unit
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω),
ESD2 testing is performed in
accordance with the Charge Device Model, Robotic (C
ZAP
= 4.0 pF).
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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