a
FEATURES
0.01% THD at +10 dBV In/Out
100 dB VCA Dynamic Range
Low VCA Control Feedthrough
100 dB Level Detection Range
Log/Antilog Control Paths
Low External Component Count
APPLICATIONS
Compressors
Expanders
Limiters
AGC Circuits
Voltage-Controlled Filters
Noise Reduction Systems
Stereo Noise Gates
Dynamic Range
Processors/Dual VCA
SSM2120/SSM2122
FUNCTIONAL BLOCK DIAGRAM
V+
36kΩ
SIGNAL
OUT
CURRENT
MIRRORS
–V
C
+V
C
V+
V+
SIGNAL
INPUT
V+
36kΩ
I
REF
GENERAL DESCRIPTION
V–
The SSM2120 is a monolithic integrated circuit designed for the
purpose of processing dynamic signals in various analog systems
including audio. This “dynamic range processor” consists of two
VCAs and two level detectors (the SSM2122 consists of two
VCAs only). These circuit blocks allow the user to logarithmically
control the gain or attenuation of the signals presented to the
level detectors depending on their magnitudes. This allows the
compression, expansion or limiting of ac signals, some of the
primary applications for the SSM2120.
PIN CONNECTIONS
22-Pin Plastic DIP
(P Suffix)
16-Pin Plastic DIP
(P Suffix)
THRESH 1 1
LOG AV 1 2
CON
OUT 1
3
SIG
OUT 1
4
+V
C1
5
CFT 1 6
22 GND
21 V+
20 SIG
OUT 2
19 +V
C2
GND 1
SIG
OUT 1
2
+V
C1
3
CFT 1 4
16 GND
15 V+
14 SIG
OUT 2
SSM2120
18 CFT 2
13 +V
C2
TOP VIEW
–V
C1
5 (Not to Scale) 12 CFT 2
11 –V
C2
10 SIG
IN 2
9 GND
SSM2122
TOP VIEW 17 –V
C2
–V
C1
7 (Not to Scale) 16 SIG
IN 2
15 REC
IN 2
14 CON
OUT 2
13 LOG AV 2
12 THRESH 2
SIG
IN 1
6
I
REF
7
V– 8
SIG
IN 1
8
REC
IN 1
9
I
REF
10
V– 11
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
SSM2120/SSM2122–SPECIFICATIONS
I
(@V = 15 V, T = +25 C,
ELECTRICAL CHARACTERISTICS
unless otherwise noted)
Parameter
POWER SUPPLY
Supply Voltage Range
Positive Supply Current
Negative Supply Current
VCAs
Max I
SIGNAL
(In/Out)
Output Offset
Control Feedthrough (Trimmed)
Gain Control Range
Control Sensitivity
Gain Scale Factor Drift
Frequency Response
Off Isolation
Current Gain
THD (Unity-Gain)
Noise (20 kHz Bandwidth)
LEVEL DETECTORS (SSM2120 ONLY)
Detection Range
Input Current Range
Rectifier Input Bias Current
Output Sensitivity (At LOG AV Pin)
Output Offset Voltage
Frequency Response
I
IN
= 1 mA p-p
I
IN
= 10
µA
p-p
I
IN
= 1
µA
p-p
CONTROL AMPLIFIERS (SSM2120 ONLY)
Input Bias Current
Output Drive (Max Sink Current)
Input Offset Voltage
Specifications are subject to change without notice.
S
A
REF
= 200 A, +V
C
= –V
C
= GND (A
V
= 0 dB). 0 dB = 1 V rms
SSM2120/SSM2122
Typ
Max
±
18
10
–8
±
350
±
8
+40
6
–3300
250
100
–0.5
0.005
–80
90
0.085
95
2800
4
3
±
0.5
1000
50
7.5
±
85
7.5
±
0.5
±
175
±
4.2
±
3.4
+0.5
0.04
Conditions
Min
±
5
Units
V
mA
mA
µA
µA
µV
dB
mV/dB
ppm/°C
kHz
dB
dB
%
dB
dB
µA
p-p
nA
mV/dB
mV
8
–6
±
300
R
IN
= R
OUT
= 36 kΩ, –30 dB
≤
A
V
≤
0 dB
Unity-Gain
–85
±
325
±
1
±
750
Unity Gain or Less
At 1 kHz
+V
C
= –V
C
= 0 V
+10 dBV IN/OUT
RE: 0 dBV
kHz
5.0
nA
mA
mV
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Operating Temperature Range . . . . . . . . . . . . –10°C to +55°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . 10 mA
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
Package Type
16-Pin Plastic DIP (P)
22-Pin Plastic DIP (P)
θ
JA1
86
70
θ
JC
10
7
Units
°C/W
°C/W
Model
SSM2120
SSM2122
Temperature
Range
–10°C to +50°C
–10°C to +50°C
Package
Description
22-Pin Plastic DIP
16-Pin Plastic DIP
Package
Option
(N-22)
(N-16)
NOTE
1
θ
JA
is specified for worst case mounting conditions, i.e.,
θ
JA
is specified for
device in socket for P-DIP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SSM2120/SSM2122 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–2–
REV. C
SSM2120/SSM2122
+V
C1
SSM2122
|I
IN
|
FULL
WAVE
RECTIFIER
2V
V+
REC
IN 1
THRESH 1
CON
OUT 1
INPUT 1
OUTPUT 1
–V
C1
+V
C2
CFT 1
LOG AV 1
V–
V+
|I
IN
|
INPUT 2
OUTPUT 2
REC
IN 2
FULL
WAVE
RECTIFIER
2V
–V
C2
CFT 2
THRESH 2
CON
OUT 2
LOG AV 2
V–
Figure 1. SSM2120 Block Diagram
VOLTAGE-CONTROLLED AMPLIFIERS
VCA PERFORMANCE
The two voltage-controlled amplifiers are full Class A current
in/current out devices with complementary dB/V gain control
ports. The control sensitivities are +6 mV/dB and –6 mV/dB. A
resistor divider (attenuator) is used to adapt the sensitivity of an
external control voltage to the range of the control port. It is
best to use 200
Ω
or less for the attenuator resistor to ground.
VCA INPUTS
Figures 2a and 2b show the typical THD and noise performance
of the VCAs over
±20
dB gain/attenuation. Full Class A operation
provides very low THD.
0.03
REFERENCE PIN
THD – %
0.003
–20
The signal inputs behave as virtual grounds. The input current
compliance range is determined by the current into the reference
current pin.
0.01
The reference current determines the input and output current
compliance range of the VCAs. The current into the reference
pin is set by connecting a resistor to V+. The voltage at the
reference pin is about two volts above V– and the current will be
–10
I
REF
=
[(V
+)
– ((V – )
+
2
V
)]
R
REF
0
GAIN – dB
10
20
The current consumption of the VCAs will be directly pro-
portional to I
REF
which is nominally 200
µA.
The device will
operate at lower current levels which will reduce the effective
dynamic range of the VCAs. With a 200
µA
reference current,
the input and output clip points will be
±
400
µA.
In general:
I
CLIP
=
±
2
I
REF
VCA OUTPUTS
NOISE – dBV
a. VCA THD Performance vs. Gain
(+10 dBV In/Out @ 1 kHz)
–70
–80
The VCA outputs are designed to interface directly with the virtual
ground inputs of external operational amplifiers configured as
current-to-voltage converters. The outputs must operate at virtual
ground because of the output stage’s finite output impedance.
The power supplies and selected compliance range determines
the values of input and output resistors needed. As an example,
with
±
15 V supplies and
±400 µA
maximum input and output
current, choose R
IN
= R
OUT
= 36 kΩ for an output compliance
range of
±
14.4 V. Note that the signal path through the VCA
including the output current-to-voltage converter is noninverting.
–90
–20
–10
0
GAIN – dB
10
20
b. VCA Noise vs. Gain (20 kHz Bandwidth)
Figure 2. Typical THD and Noise Performance
REV. C
–3–
SSM2120/SSM2122
TRIMMING THE VCAs
The control feedthrough (CFT) pins are optional control feed-
through null points. CFT nulling is usually required in applications
such as noise gating and downward expansion. If trimming is
not used, leave the CFT pins open.
Trim Procedure
1. Apply a 100 Hz sine wave to the control point attenuator.
The signal peaks should correspond to the control voltages
which induce the VCAs maximum intended gain and at least
30 dB of attenuation.
2. Adjust the 50 kΩ potentiometer for the minimum
feedthrough.
(Trimmed control feedthrough is typically well under 1 mV rms
when the maximum gain is unity using 36 kΩ input and output
resistors.)
Applications such as compressor/limiters typically do not require
control feedthrough trimming because the VCA operates at
unity-gain unless the signal is large enough to initiate gain
reduction. In this case the signal masks control feedthrough.
This trim is ineffective for voltage-controlled filter applications.
LEVEL DETECTION CIRCUITS
Note: It is natural to assume that with the addition of the
averaging capacitor, the LOG AV output would become the
average of the log of the absolute value of I
IN
. However, since the
capacitor forces an ac ground at the emitter of the output
transistor, the capacitor charging currents are proportional to
the
antilog
of the voltage at the base of the output transistor.
Since the base voltage of the output transistor is the log of the
absolute value of I
IN
, the log and antilog terms cancel, so the
capacitor becomes a linear integrator with a charging current
directly proportional to the absolute value of the input current.
This effectively inverts the order of the averaging and logging
functions. The signal at the output therefore is the
log of the
average of the absolute value of I
IN
.
USING DETECTOR PINS REC
IN
, LOG
AV
, THRESH AND
CON
OUT
When applying signals to REC
IN
(rectifier input) an input series
resistor should be followed by a low leakage blocking capacitor
since REC
IN
has a dc voltage of approximately 2.1 V above
ground. Choose R
IN
for a
±
1.5 mA peak signal. For
±
15 V
operation this corresponds to a value of 10 kΩ.
A 1.5 MΩ value of R
REF
from log average to –15 V will establish
a 10
µA
reference current in the logging transistor (Q
1
). This
will bias the transistor in the middle of the detector’s dynamic
current range in dB to optimize dynamic range and accuracy.
The LOG AV outputs are buffered and amplified by unipolar
drive op amps. The 39 kΩ, 1 kΩ resistor network at the
THRESH pin provides a gain of 40.
An attenuator from the CON
OUT
(control output) to the
appropriate VCA control port establishes the control sensitivity.
Use 200
Ω
for the attenuator resistor to ground and choose
R
CON
for the desired sensitivity. Care should be taken to minimize
capacitive loads on the control outputs CON
OUT
. If long lines
or capacitive loads are present, it is best to connect the series
resistor R
CON
as closely to the CON
OUT
pin as possible.
DYNAMIC LEVEL DETECTOR CHARACTERISTICS
The SSM2120 contains two independent level detection
circuits. Each circuit contains a wide dynamic range full-wave
rectifier, logging circuit and a unipolar drive amplifier. These
circuits will accurately detect the input signal level over a
100 dB range from 30 nA to 3 mA peak-to-peak.
LEVEL DETECTOR THEORY OF OPERATION
Referring to the level detector block diagram of Figure 3, the
REC
IN
input is an AC virtual ground. The next block imple-
ments the full-wave rectification of the input current. This
current is then fed into a logging transistor (Q
1
) whose pair
transistor (Q
2
) has a fixed collector current of I
REF
. The LOG
AV output is then:
V
LOG
AV
=
kT
|I
IN
|
ln
q
I
REF
With the use of the LOG AV capacitor the output is then the log
of the average of the absolute value of I
IN
.
(The unfiltered LOG AV output has broad flat plateaus with
sharp negative spikes at the zero crossing. This reduces the
“work” that the averaging capacitor must do, particularly at low
frequencies.)
Figures 4 and 5 show the dynamic performance of the level
detector to a change in signal level. The input to the detector (not
shown) is a series of 500 ms tone bursts at 1 kHz in successive
10 dBV steps. The tone bursts start at a level of –60 dBV (with
R
IN
= 10 k) and return to –60 dBV after each successive 10 dB
step. Tone bursts range from –60 dBV to +10 dBV. Figure 4
shows the logarithmic level detector output. The output of the
detector is 3 mV/dB at LOG AV and the amplifier gain is 40
which yields 120 mV/dB. Thus, the output at CON
OUT
is seen
to increase by 1.2 V for each 10 dBV increase in input level.
1kΩ
39kΩ
V+
R
IN
INPUT
REC
IN
|I
I N
|
FULL
WAVE
RECTIFIER
Q1
2V
LOG AV
C
AV
Q2
I
REF
THRESH
CON
OUT
R
CON
TO V
C
200Ω
V–
R
REF
V–
Figure 3. Level Detector
–4–
REV. C
SSM2120/SSM2122
2V
100
90
1s
The decay rates are linear ramps that are dependent on the
current out of the LOG AV pin (set by R
REF
) and the value of
C
AV
. The integration or decay time of the circuit is derived from
the formula:
Decrementation Rate (in dB/s) =
I
REF
×
333
C
AV
10
0%
Table I. Settling Time (t
S
) for C
AV
= 10 F. t
S
= t
S
(C
AV
= 10 F)
5 dB
Figure 4. Detector Output
2V
100
90
3 dB
21.46
26.83
28.33
27.79
2 dB
30.19
35.56
37.06
37.52
(+144
µs)
(+46
µs)
1 dB
46.09
51.46
52.96
53.42
10 dB Step
20 dB Step
30 dB Step
40 dB Step
50 dB Step
60 dB Step
11.28 ms
16.65
18.15
18.61
APPLICATIONS
10
0%
50ms
The following applications for the SSM2120 use both the VCAs
and level detectors in conjunction to assimilate a variety of
functions.
The first section describes the arrangement of the threshold
control in each control circuit configuration. These control
circuits form the foundation for the applications to follow which
include the downward expander, compressor/limiter and
compandor.
THRESHOLD CONTROL
Figure 5. Overlayed Detector Output
DYNAMIC ATTACK AND DECAY RATES
Figure 5 shows the output levels overlayed using a storage
scope. The attack rate is determined by the step size and the
value of C
AV
. The attack time to final value is a function of the
step size increase. Table I shows the values of total settling
times to within 5 dB, 3 dB, 2 dB and 1 dB of final value with
C
AV
= 10
µF.
When step sizes exceed 40 dB, the increase in
settling time for larger steps is negligible. To calculate the attack
time to final value for any value of C
AV
, simply multiply the
value in the chart by C
AV
/10
µF.
Figure 6a shows the control circuit for a typical downward
expander while Figure 6b shows a typical control curve. Here,
the threshold potentiometer adjusts V
T
to provide a negative
unipolar control output. This is typically used in noise gate,
downward expander, and dynamic filter applications. This
potentiometer is used in all applications to control the signal
level versus control voltage characteristics.
THRESHOLD
R
IN
L
V+
MONO
OR R
R
IN
REC
IN
|I
IN
|
R
LL
THRESHOLD
CONTROL
V
T
R
T
TO +V
C
1kΩ
2V
200Ω
V
CON
V–
CON
OUT
R
CON
+
39kΩ
MONO – R
IN
= 10kΩ
STEREO – R
IN
= 20kΩ
LOG AV
–
C
AV
V–
1.5MΩ
V–
*
*LOWER LIMIT CAN BE FIXED
BY CONNECTING A RESISTOR
R
LL
FROM REC
IN
TO GROUND
V
IN
– dB
b. Typical Downward Expander
Control Curve
Figure 6. Noise Gate/Downward Expander Control Circuit and Typical Response
a. Control Circuit
REV. C
–5–
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