EEWORLDEEWORLDEEWORLD

Part Number

Search

V61C16F35

Description
Standard SRAM, 2KX8, 35ns, CMOS, PDSO24
Categorystorage    storage   
File Size300KB,8 Pages
ManufacturerMosel Vitelic Corporation ( MVC )
Websitehttp://www.moselvitelic.com
Download Datasheet Parametric View All

V61C16F35 Overview

Standard SRAM, 2KX8, 35ns, CMOS, PDSO24

V61C16F35 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid101232311
package instructionSOP, SOP24,.4
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time35 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G24
JESD-609 codee0
memory density16384 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of terminals24
word count2048 words
character code2000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP24,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum standby current0.0001 A
Minimum standby current4.5 V
Maximum slew rate0.08 mA
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
TI uses AEC-Q100 Grade-0 digital isolators to overcome high temperature isolation design
[i=s]This post was last edited by qwqwqw2088 on 2020-10-30 15:22[/i]As 48-V hybrid vehicles become more popular in the automotive industry, the need for in-vehicle network signal isolation becomes mor...
qwqwqw2088 Analogue and Mixed Signal
DC-DC output voltage error
According to the schematic diagram of the example, as long as the input voltage exceeds 12V, the output voltage begins to increase linearly and does not stabilize at 5V output. What's going on? Thank ...
xiaxingxing Analog electronics
【GD32E503 Review】 UART Communication Experiment
I have been conducting serial communication experiments these days. The serial port sending test was normal, but the receiving test failed. Even if I used the example compilation and download test, I ...
hujj Domestic Chip Exchange
DM8148 hardware introduction and MCFW software architecture description
DM8148 hardware introduction and MCFW software architecture description...
灞波儿奔 DSP and ARM Processors
Huawei architect explains: HarmonyOS low-latency and high-reliability message transmission principle
Author: zhangkesi, Huawei Software Architecture Design EngineerThis is an introduction to the low-latency and high-reliability message transmission principle of HarmonyOS. I hope it will be helpful to...
天明 Embedded System
LVDS Receive
I am using Cyclone V FPGA to receive 8-channel differential data, 12bit, 600M data rate. The data received by LVDS_RX core is incorrect. The 8-channel data is not synchronized. Can anyone tell me how ...
BIT_Wang Altera SoC

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号