Specifications
GAL16V8
High Performance E
2
CMOS PLD
Generic Array Logic™
FEATURES
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/Guaranteed 100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 20-pin PAL
®
Devices with Full Func-
tion/Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
FUNCTIONAL BLOCK DIAGRAM
I/CLK
CLK
GAL16V8
8
I
8
I
OLMC
I/O/Q
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 32)
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
I
8
I
OLMC
OE
OLMC
I/O/Q
I/O/Q
I/OE
DESCRIPTION
The GAL16V8C, at 5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
2
) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL16V8 are the PAL architectures
listed in the table of the macrocell description section. GAL16V8
devices are capable of emulating any of these PAL architectures
with full function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor guarantees 100% field programmability
and functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are guaranteed.
PIN CONFIGURATION
DIP
PLCC
I
I
2
I
I
I
I
I
8
14
9
I
GND
11
I/OE I/O/Q
13
6
4
I/CLK Vcc
20
18
I/O/Q
I/O/Q
I/CLK
I
I
I
1
20
Vcc
I/O/Q
I/O/Q
GAL16V8
16
I/O/Q
GAL
16V8
5
15
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/O/Q
I/O/Q
I/O/Q
Top View
I
I
I
I/O/Q
I
GND
10
11
I/OE
Copyright © 1996 Lattice Semiconductor Corporation. E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, L with Lattice Semiconductor Corp. and L (Stylized) are registered
trademarks of Lattice Semiconductor Corporation (LSC). The LSC Logo, Generic Array Logic, In-System Programmability, In-System Programmable, ISP, ispATE, ispCODE, ispDOWNLOAD,
ispGDS, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice
Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.lattice.com
1996 Data Book
1996 Data Book
3-65
Specifications
GAL16V8
GAL16V8 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)
5
Tsu (ns)
3
Tco (ns)
4
Icc (mA)
115
115
Ordering #
GAL16V8C-5LP
GAL16V8C-5LJ
GAL16V8C-7LP
GAL16V8C-7LJ
GAL16V8B-7LP
GAL16V8B-7LJ
GAL16V8B-10LP
GAL16V8B-10LJ
GAL16V8B-15QP
GAL16V8B-15QJ
GAL16V8B-15LP
GAL16V8B-15LJ
GAL16V8B-25QP
GAL16V8B-25QJ
GAL16V8B-25LP
GAL16V8B-25LJ
Package
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
7.5
7
5
115
115
115
115
10
10
7
115
115
15
12
10
55
55
90
90
25
15
12
55
55
90
90
Industrial Grade Specifications
Tpd (ns)
7.5
Tsu (ns)
7
Tco (ns)
5
Icc (mA)
130
130
Ordering #
GAL16V8C-7LPI
GAL16V8C-7LJI
GAL16V8B-10LPI
GAL16V8B-10LJI
GAL16V8B-15LPI
GAL16V8B-15LJI
GAL16V8B-20QPI
GAL16V8B-20QJI
GAL16V8B-25QPI
GAL16V8B-25QJI
GAL16V8B-25LPI
GAL16V8B-25LJI
Package
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Plastic DIP
20-Lead PLCC
10
10
7
130
130
15
12
10
130
130
20
13
11
65
65
25
15
12
65
65
130
130
PART NUMBER DESCRIPTION
XXXXXXXX _ XX
X
X X
GAL16V8C
Device Name
GAL16V8B
Speed (ns)
L = Low Power
Q = Quarter Power
Power
Grade
Blank = Commercial
I = Industrial
Package
P = Plastic DIP
J = PLCC
3-66
1996 Data Book
Specifications
GAL16V8
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is ac-
complished by development software/hardware and is completely
transparent to the user.
There are three global OLMC configuration modes possible:
simple, complex,
and
registered.
Details of each of these
modes are illustrated in the following pages. Two global bits, SYN
and AC0, control the mode configuration for all macrocells. The
XOR bit of each macrocell controls the polarity of the output in any
of the three modes, while the AC1 bit of each of the macrocells
controls the input/output configuration. These two global and 16
individual architecture bits define all possible configurations in a
GAL16V8 . The information given on these architecture bits is
only to give a better understanding of the device. Compiler soft-
ware will transparently set these architecture bits from the pin
definitions, so the user should not need to directly manipulate
these architecture bits.
The following is a list of the PAL architectures that the GAL16V8
can emulate. It also shows the OLMC mode under which the
GAL16V8 emulates the PAL architecture.
PAL Architectures
Emulated by GAL16V8
16R8
16R6
16R4
16RP8
16RP6
16RP4
16L8
16H8
16P8
10L8
12L6
14L4
16L2
10H8
12H6
14H4
16H2
10P8
12P6
14P4
16P2
GAL16V8
Global OLMC Mode
Registered
Registered
Registered
Registered
Registered
Registered
Complex
Complex
Complex
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OLMC
modes as different device types. These device types are listed
in the table below. Most compilers have the ability to automati-
cally select the device type, generally based on the register usage
and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. The different device types listed in the table
can be used to override the automatic device selection by the
software. For further details, refer to the compiler software
manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.
Registered
ABEL
CUPL
LOG/iC
OrCAD-PLD
PLDesigner
TANGO-PLD
P16V8R
G16V8MS
GAL16V8_R
"Registered"
1
P16V8R
2
G16V8R
Complex
P16V8C
G16V8MA
GAL16V8_C7
"Complex"
1
P16V8C
2
G16V8C
Simple
P16V8AS
G16V8AS
GAL16V8_C8
"Simple"
1
P16V8C
2
G16V8AS
3
Auto Mode Select
P16V8
G16V8
GAL16V8
GAL16V8A
P16V8A
G16V8
In
registered mode
pin 1 and pin 11 are permanently configured
as clock and output enable, respectively. These pins cannot be
configured as dedicated inputs in the registered mode.
In
complex mode
pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In
simple mode
all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
1) Used with
Configuration
keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
3-67
1996 Data Book
Specifications
GAL16V8
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations
of polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/O's are possible in this
mode. Dedicated input or output functions can be implemented
as subsets of the I/O function.
Registered outputs have eight product terms per output. I/O's
have seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.
CLK
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.
D
Q
Q
XOR
OE
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
3-68
1996 Data Book
Specifications
GAL16V8
REGISTERED MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
0
0000
4
8
12
16
20
24
28
2128
PTD
OLMC
0224
19
2
0256
XOR-2048
AC1-2120
OLMC
0480
18
3
0512
XOR-2049
AC1-2121
OLMC
0736
17
4
0768
XOR-2050
AC1-2122
OLMC
0992
16
5
1024
XOR-2051
AC1-2123
OLMC
1248
15
6
1280
XOR-2052
AC1-2124
OLMC
1504
14
7
1536
XOR-2053
AC1-2125
OLMC
1760
13
8
1792
XOR-2054
AC1-2126
OLMC
2016
12
9
2191
XOR-2055
AC1-2127
OE
11
SYN-2192
AC0-2193
3-69
1996 Data Book
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