Multiformat SDTV Video Decoder with Fast
Switch Overlay Support
ADV7184
FEATURES
Multiformat video decoder supports NTSC-(J, M, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates four 54 MHz, 10-bit ADCs
SCART fast blank support
Clocked from a single 28.63636 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive digital line length tracking (ADLLT™), signal
processing, and enhanced FIFO management give mini
TBC functionality
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
CTI (chroma transient improvement)
DNR (digital noise reduction)
Multiple programmable analog input formats
CVBS (composite video)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and Betacam)
12 analog video input channels
Integrated antialiasing filters
Automatic NTSC/PAL/SECAM identification
Programmable interrupt request output pin
Digital output formats (8-bit or 16-bit)
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD 0.5 V
to 1.6 V analog signal input range
Differential gain: 0.5% typ
Differential phase: 0.5° typ
Programmable video controls
Peak white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free-run mode (generates stable video output with no I/P)
VBI decode support for closed captioning (including XDS),
WSS, CGMS, Gemstar® 1×/2×, Teletext, VITC, VPS
Power-down mode
2-wire serial MPU interface (I
2
C®-compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Industrial temperature grade: –40°C to +85°C
80-lead LQFP Pb-free package
APPLICATIONS
DVD recorders
Video projectors
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
AVR receivers
GENERAL DESCRIPTION
The ADV7184 integrated video decoder automatically detects
and converts a standard analog baseband television signal,
which is compatible with worldwide standards NTSC, PAL,
and SECAM, into 4:2:2 component video data-compatible
with 16-bit or 8-bit CCIR601/CCIR656.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in line-
locked clock-based systems. This makes the device ideally
suited for a broad range of applications with diverse analog video
characteristics, including tape-based sources, broadcast sources,
security and surveillance cameras, and professional systems.
The 10-bit accurate ADC provides professional quality video
performance and is unmatched. This allows true 8-bit
resolution in the 8-bit output mode.
The 12 analog input channels accept standard composite,
S-Video, and YPrPb video signals in an extensive number of
combinations.
AGC and clamp restore circuitry allow an input video signal
peak-to-peak range of 0.5 V to 1.6 V. Alternatively, these can be
bypassed for manual settings.
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7184 modes
are set up over a 2-wire, serial, bidirectional port (I
2
C-
compatible).
SCART and overlay functionality are enabled by the ADV7184’s
ability to simultaneously process CVBS and standard definition
RGB signals. Signal mixing is controlled by the fast blank pin.
The ADV7184 is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7184 is packaged in a
small 80-lead LQFP Pb-free package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
ADV7184
TABLE OF CONTENTS
Introduction ...................................................................................... 4
Analog Front End ......................................................................... 4
Standard Definition Processor (SDP)........................................ 4
Electrical Characteristics ................................................................. 5
Video Specifications..................................................................... 6
Timing Specifications .................................................................. 7
Analog Specifications................................................................... 7
Thermal Specifications ................................................................ 8
Timing Diagrams.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
Package Thermal Performance................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Analog Front End ........................................................................... 12
Analog Input Muxing ................................................................ 12
Manual Input Muxing................................................................ 14
XTAL Clock Input Pin Functionality....................................... 15
28.63636 MHz Crystal Operation ............................................ 15
Antialiasing Filters ..................................................................... 15
SCART and Fast Blanking......................................................... 15
Fast Blank Control...................................................................... 16
Readback of FB Pin Status......................................................... 18
Global Control Registers ............................................................... 19
Power-Save Modes...................................................................... 19
Reset Control .............................................................................. 19
Global Pin Control ..................................................................... 19
Global Status Registers................................................................... 21
Standard Definition Processor (SDP).......................................... 22
SD Luma Path ............................................................................. 22
SD Chroma Path......................................................................... 22
Sync Processing........................................................................... 23
VBI Data Recovery..................................................................... 23
General Setup.............................................................................. 23
Color Controls ............................................................................ 25
Clamp Operation........................................................................ 27
Luma Filter .................................................................................. 28
Chroma Filter.............................................................................. 31
Gain Operation........................................................................... 31
Chroma Transient Improvement (CTI) .................................. 34
Digital Noise Reduction (DNR), and Luma Peaking Filter .. 35
Comb Filters................................................................................ 36
AV Code Insertion and Controls ............................................. 39
Synchronization Output Signals............................................... 40
Sync Processing .......................................................................... 48
VBI Data Decode ....................................................................... 48
I
2
C Readback registers ............................................................... 57
Pixel Port Configuration ............................................................... 71
MPU Port Description................................................................... 72
Register Accesses ........................................................................ 73
Register Programming............................................................... 73
I
2
C Sequencer.............................................................................. 73
I
2
C Register Maps ........................................................................... 74
User Map ..................................................................................... 74
User Sub Map.............................................................................. 90
I
2
C Programming Examples.......................................................... 99
Mode 1 CVBS Input................................................................... 99
Mode 2 S-Video Input ............................................................. 100
Mode 3 525i/625i YPrPb Input .............................................. 101
Mode 4 SCART—S-Video or CVBS Autodetect.................. 102
Mode 5 SCART Fast Blank—CVBS and RGB...................... 103
Mode 6 SCART RGB input (Static Fast Blank)—CVBS and
RGB ............................................................................................ 104
Rev. 0 | Page 2 of 108
ADV7184
PCB Layout Recommendations ................................................. 105
Analog Interface Inputs........................................................... 105
Power Supply Decoupling ....................................................... 105
PLL ............................................................................................. 105
Digital Outputs (Both Data and Clocks) .............................. 105
Digital Inputs.............................................................................106
XTAL And Load Capacitor Values Selection ........................106
Typical Circuit Connection .........................................................107
Outline Dimensions......................................................................108
Ordering Guide .........................................................................108
REVISION HISTORY
7/05—Revision 0: Initial Version
Rev. 0 | Page 3 of 108
ADV7184
INTRODUCTION
The ADV7184 is a high quality, single chip, multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-Video, and
component video into a digital ITU-R BT.656 format.
The advanced and highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock-based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape-based sources, broadcast sources,
security and surveillance cameras, and professional systems.
STANDARD DEFINITION PROCESSOR (SDP)
The ADV7184 is capable of decoding a large selection of
baseband video signals in composite, S-Video, and component
formats. The video standards supported include PAL B/D/I/G/H,
PAL60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and
SECAM B/D/G/K/L. The ADV7184 can automatically detect
the video standard and process it accordingly.
The ADV7184 has a 5-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
standard and signal quality without user intervention. Video
user controls such as brightness, contrast, saturation, and hue
are also available within the ADV7184.
The ADV7184 implements a patented adaptive digital line-
length tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7184 to track and decode poor quality video sources such
as VCRs, noisy sources from tuner outputs, VCD players, and
camcorders. The ADV7184 contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
The ADV7184 can process a variety of VBI data services, such
as closed captioning (CC), wide screen signaling (WSS), copy
generation management system (CGMS), Gemstar 1×/2×,
extended data service (XDS), and teletext. The ADV7184 is
fully Macrovision certified; detection circuitry enables Type I,
II, and III protection levels to be identified and reported to the
user. The decoder is also fully robust to all Macrovision signal
inputs.
ANALOG FRONT END
The ADV7184 analog front end includes four 10-bit ADCs
that digitize the analog video signal before applying it to the
standard definition processor. The analog front end uses
differential channels to each ADC to ensure high performance
in mixed-signal applications.
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7184. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping within the ADV7184. The
ADCs are configured to run in 4× oversampling mode.
The ADV7184 has optional antialiasing filters on each of the
four input channels. The filters are designed for SD video with
approximately 6 MHz bandwidth.
SCART and overlay functionality are enabled by the ADV7184’s
ability to simultaneously process CVBS and Standard Definition
RGB signals. Signal mixing is controlled by the Fast Blank pin.
FUNCTIONAL BLOCK DIAGRAM
CLAMP
AIN1–
AIN12
12
INPUT
MUX
CLAMP
ANTI
ALIAS
FILTER
ANTI
ALIAS
FILTER
ANTI
ALIAS
FILTER
10
A/D
10
A/D
10
A/D
10
DECIMATION AND 10
DOWNSAMPLING
10
FILTERS
10
CVBS/Y
LUMA
FILTER
LUMA
RESAMPLE
ANTI
ALIAS
FILTER
10
A/D
DATA
PREPROCESSOR
STANDARD DEFINITION PROCESSOR
LUMA
2D COMB Y
(5H MAX)
16
F
SC
RECOVERY
CVBS
CHROMA
C
DEMOD
Cr
Cb
R
G
COLORSPACE
CONVERSION
B
SYNC
EXTRACT
RESAMPLE
CONTROL
CHROMA Cr
2D COMB Cb
(4H MAX)
HS
8
8
PIXEL
DATA
P15-P8
P7-P0
CVBS
S-VIDEO
YPrPb
SCART - (RGB + CVBS)
CLAMP
OUTPUT FORMATTER
CLAMP
CHROMA
FILTER
CHROMA
RESAMPLE
FAST BLANK
OVERLAY
CONTROL
AND
AV CODE
INSERTION
VS
FIELD
SYNC PROCESSING AND
CLOCK GENERATION
FB
SYNC AND
CLK CONTROL
Y
Cr
Cb
LLC1
LLC2
ADV7184
VBI DATA RECOVERY
SCLK
SDA
ALSB
SERIAL INTERFACE
CONTROL AND VBI DATA
MACROVISION
DETECTION
GLOBAL CONTROL
STANDARD
AUTODETECTION
SYNTHESIZED
LLC CONTROL
FREE RUN
OUTPUT CONTROL
SFL
CONTROL
AND DATA
INT
Figure 1.
Rev. 0 | Page 4 of 108
05479-001
ADV7184
ELECTRICAL CHARACTERISTICS
At A
VDD
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDDIO
= 3.0 V to 3.6 V, P
VDD
= 1.71 V to 1.89 V, nominal input range 1.6 V.
Operating temperature range, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
1, 2, 3
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage
4
Input Low Voltage
5
Input Current
Input Capacitance
9
DIGITAL OUTPUTS
Output High Voltage
8
Output Low Voltage
8
High Impedance Leakage Current
Output Capacitance
9
POWER REQUIREMENTS
9
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Core Supply Current
Digital I/O Supply Current
PLL Supply Current
Analog Supply Current
Power-Down Current
Power-Up Time
1
2
Symbol
N
INL
DNL
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
LEAK
C
OUT
D
VDD
D
VDDIO
P
VDD
A
VDD
I
DVDD
I
DVDDIO
I
PVDD
I
AVDD
I
PWRDN
t
PWRUP
Test Conditions
Min
Typ
Max
10
±3
-0.99/2.5
Unit
Bits
LSB
LSB
V
V
μA
μA
pF
V
V
μA
pF
V
V
V
V
mA
mA
mA
mA
mA
mA
ms
BSL at 54 MHz
BSL at 54 MHz
2
Pins listed in Note 6
All other pins
7
–50
–10
–0.6/+0.7
−0.5/+0.5
0.8
+50
+10
10
I
SOURCE
= 0.4 mA
I
SINK
= 3.2 mA
2.4
0.4
10
20
1.65
3.0
1.71
3.15
1.8
3.3
1.8
3.3
105
4
11
99
269
0.65
20
2
3.6
1.89
3.45
CVBS input
10
YPrPb input
11
All ADC linearity tests performed at input range of full scale – 12.5%, and at zero scale +12.5%.
Max INL and DNL specifications obtained with part configured for component video input.
3
Temperature range T
MIN
to T
MAX
, –40°C to +85°C. The min/max specifications are guaranteed over this range.
4
To obtain specified V
IH
level on Pin 29, Register 0x13 (write only) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00, then V
IH
on
Pin 29 = 1.2 V.
5
To obtain specified V
IL
level on Pin 29, Register 0x13 (write only) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00, then V
IL
on
Pin 29 = 0.4 V.
6
Pins: 36 and 79.
7
Excluding all “TEST” pins (TEST0 to TEST12)
8
V
OH
and V
OL
levels obtained using default drive strength value (0xD5) in register subaddress 0xF4.
9
Guaranteed by characterization.
10
ADC0 powered on only.
11
All four ADCs powered on.
Rev. 0 | Page 5 of 108
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