a
FEATURES
16 8 High Speed Nonblocking Switch Arrays
AD8110: G = +1
AD8111: G = +2
Serial or Parallel Switch Array Control
Serial Data Out Allows “Daisy Chaining” of Multiple
Crosspoints to Create Larger Switch Arrays
Pin Compatible with AD8108/AD8109 8 8 Switch
Arrays
For a 16 16 Array See AD8116
Complete Solution
Buffered Inputs
Eight Output Amplifiers, AD8110 (G = +1),
AD8111 (G = +2)
Drives 150 Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.02% Differential Gain Error (R
L
= 150 )
0.02 Differential Phase Error (R
L
= 150 )
Excellent AC Performance
260 MHz –3 dB Bandwidth
500 V/ s Slew Rate
Low Power of 50 mA
Low All Hostile Crosstalk of –78 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple
Device Outputs
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Power-
On” Reset Capability)
Excellent ESD Rating: Exceeds 4000 V Human Body
Model
80-Lead TQFP Package (12 mm 12 mm)
APPLICATIONS
Routing of High Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM)
Component Video (YUV, RGB)
Compressed Video (MPEG, Wavelet)
3-Level Digital Video (HDB3)
PRODUCT DESCRIPTION
CLK
260 MHz, 16 8 Buffered
Video Crosspoint Switches
AD8110/AD8111*
FUNCTIONAL BLOCK DIAGRAM
SER/PAR
D0 D1 D2 D3 D4
A0
A1
A2
40-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
40
PARALLEL LATCH
40
8
DECODE
5:16 DECODERS
OUTPUT
BUFFER
G = +1,
G = +2
8
SET INDIVIDUAL OR
RESET ALL OUTPUTS
TO "OFF"
ENABLE/DISABLE
DATA IN
UPDATE
CE
RESET
DATA OUT
AD8110/AD8111
128
SWITCH
MATRIX
16 INPUTS
8 OUTPUTS
phase of better than 0.02% and 0.02° respectively, along with
0.1 dB flatness out to 60 MHz, make the AD8110/AD8111 ideal
for video signal switching.
The AD8110 and AD8111 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8110 has a gain of +1, while the AD8111
offers a gain of +2. They operate on voltage supplies of
±
5 V
while consuming only 50 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate “daisy chaining” of several devices) or via a paral-
lel control, allowing updating of an individual output without re-
programing the entire array.
The AD8110/AD8111 is packaged in an 80-lead TQFP package
and is available over the extended industrial temperature range
of –40°C to +85°C.
The AD8110 and AD8111 are high speed 16
×
8 video cross-
point switch matrices. They offer a –3 dB signal bandwidth
greater than 260 MHz, and channel switch times of less than
25 ns with 1% settling. With –78 dB of crosstalk and –97 dB
isolation (@ 5 MHz), the AD8110/AD8111 are useful in many
high speed applications. The differential gain and differential
*Patent
Pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
AD8110/AD8111–SPECIFICATIONS
(V =
S
5 V, T
A
= +25 C, R
L
= 1 k
Min
AD8110/AD8111
Typ
390/260
150
5
500
40
60/40
65/40
80/57
70/57
0.01
0.02
0.01
0.02
78/85
70/80
93/99
15
0.04/0.1
0.15/0.25
unless otherwise noted)
Max
Units
MHz
MHz
ns
V/µs
ns
MHz
MHz
MHz
MHz
%
%
Degrees
Degrees
dB
dB
dB
nV/
√
Hz
0.07/0.5
0.02/1.0
0.09/1.0
%
%
%
%
ppm/°C
Ω
MΩ
pF
µA
V
mA
mA
20
mV
µV/°C
V
pF
MΩ
µA
ns
ns
mV p-p
mA
mA
mA
mA
mA
V
dB
dB
°C
°C/W
23, 29
20, 26
Reference
Figure No.
6, 12
6, 12
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Propagation Delay
Slew Rate
Settling Time
Gain Flatness
Conditions
200 mV p-p, R
L
= 150
Ω
2 V p-p, R
L
= 150
Ω
2 V p-p, R
L
= 150
Ω
2 V Step, R
L
= 150
Ω
0.1%, 2 V Step, R
L
= 150
Ω
0.05 dB, 200 mV p-p, R
L
= 150
Ω
0.05 dB, 2 V p-p, R
L
= 150
Ω
0.1 dB, 200 mV p-p, R
L
= 150
Ω
0.1 dB, 2 V p-p, R
L
= 150
Ω
NTSC or PAL, R
L
= 1 kΩ
NTSC or PAL, R
L
=150
Ω
NTSC or PAL, R
L
= 1 kΩ
NTSC or PAL, R
L
= 150
Ω
f
= 5 MHz
f
= 10 MHz
f
= 10 MHz, R
L
=150
Ω,
One Channel
0.01 MHz to 50 MHz
R
L
= 1 kΩ
R
L
= 150
Ω
No Load, Channel-Channel
R
L
= 1 kΩ, Channel-Channel
300/190
11, 17
6, 12
6, 12
6, 12
6, 12
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Crosstalk, All Hostile
Off Isolation, Input-Output
Input Voltage Noise
DC PERFORMANCE
Gain Error
Gain Matching
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Impedance
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
Output Current
Short Circuit Current
INPUT CHARACTERISTICS
Input Offset Voltage
Input Voltage Range
Input Capacitance
Input Resistance
Input Bias Current
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time, 2 V Step
Switching Transient (Glitch)
POWER SUPPLIES
Supply Current
7, 13
7, 13
22, 28
19, 25
0.5/8
DC, Enabled
Disabled
Disabled
Disabled, AD8110 Only
No Load
0.2
10/0.001
2
1/NA
±
3
40
65
±
2.5
20
Worse Case (All Configurations)
Temperature Coefficient
Any Switch Configuration
Per Output Selected
5
12
±
2.5/± 1.25
±
3/± 1.5
2.5
1
10
2
60
25
20/30
38
15
38
15
11
±
4.5 to
±5.5
75/78
–55/–58
–40 to +85
48
34, 40
35, 41
5
50%
UPDATE
to 1% Settling
Measured at Output
AVCC, Outputs Enabled, No Load
AVCC, Outputs Disabled
AVEE, Outputs Enabled, No Load
AVEE, Outputs Disabled
DVCC
f
= 100 kHz
f
= 1 MHz
Operating (Still Air)
Operating (Still Air)
21, 27
Supply Voltage Range
PSRR
OPERATING TEMPERATURE RANGE
Temperature Range
θ
JA
Specifications subject to change without notice.
18, 24
–2–
REV. 0
AD8110/AD8111
TIMING CHARACTERISTICS (Serial)
Parameter
Serial Data Setup Time
CLK Pulsewidth
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK to
UPDATE
Delay
UPDATE
Pulsewidth
CLK to DATA OUT Valid, Serial Mode
Propagation Delay,
UPDATE
to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK,
UPDATE
Rise and Fall Times
RESET
Time
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
–
–
–
–
Min
20
100
20
100
0
50
180
8
8
100
200
Limit
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
1
CLK
0
1
DATA IN
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
t
2
t
4
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
OUT7 (D3)
OUT00 (D0)
t
1
t
3
OUT7 (D4)
t
5
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
6
t
7
DATA OUT
Figure 1. Timing Diagram, Serial Mode
Table I. Logic Levels
V
IH
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
2.0 V min
V
IL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
0.8 V max
V
OH
V
OL
I
IH
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
20
µA
max
I
IL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
–400
µA
min
I
OH
I
OL
DATA OUT
2.7 V min
DATA OUT
0.5 V max
DATA OUT
–400
µA
max
DATA OUT
3.0 mA min
REV. 0
–3–
AD8110/AD8111
TIMING CHARACTERISTICS (Parallel)
Limit
Parameter
Data Setup Time
CLK Pulsewidth
Data Hold Time
CLK Pulse Separation
CLK to
UPDATE
Delay
UPDATE
Pulsewidth
Propagation Delay,
UPDATE
to Switch On or Off
CLK,
UPDATE
Rise and Fall Times
RESET
Time
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
–
–
–
Min
20
100
20
100
0
50
8
100
200
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
2
1
CLK
0
t
4
t
1
D0–D4
A0–A2
1
0
t
3
t
5
1 = LATCHED
UPDATE
0 = TRANSPARENT
t
6
Figure 2. Timing Diagram, Parallel Mode
Table II. Logic Levels
V
IH
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2
CE, UPDATE
2.0 V min
V
IL
V
OH
V
OL
I
IH
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2
CE, UPDATE
20
µA
max
I
IL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2
CE, UPDATE
–400
µA
min
I
OH
I
OL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2
CE, UPDATE
DATA OUT
0.8 V max
2.7 V min
DATA OUT
0.5 V max
DATA OUT
–400
µA
max
DATA OUT
3.0 mA min
–4–
REV. 0
AD8110/AD8111
ABSOLUTE MAXIMUM RATINGS
1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V
Internal Power Dissipation
2
AD8110/AD8111 80-Lead Plastic TQFP (ST) . . . . . 2.6 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± V
S
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air (T = +25°C):
A
80-lead plastic TQFP (ST):
θ
JA
= 48°C/W.
The maximum power that can be safely dissipated by the
AD8110/AD8111 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for plas-
tic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the pack-
age. Exceeding a junction temperature of +175°C for an ex-
tended period can result in device failure.
While the AD8110/AD8111 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junc-
tion temperature (+150°C) is not exceeded under all condi-
tions. To ensure proper operation, it is necessary to observe the
maximum power derating curves shown in Figure 3.
5.0
MAXIMUM POWER DISSIPATION – Watts
T
J
= 150 C
4.0
3.0
2.0
1.0
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70
AMBIENT TEMPERATURE – C
80 90
Figure 3. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Temperature
Range
–40°C to +85°C
–40°C to +85°C
Package
Description
80-Lead Plastic TQFP (12 mm
×
12 mm)
80-Lead Plastic TQFP (12 mm
×
12 mm)
Evaluation Board
Evaluation Board
Package
Option
ST-80A
ST-80A
Model
AD8110AST
AD8111AST
AD8110-EB
AD8111-EB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8110/AD8111 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
京公网安备 11010802033920号
EEWORLD
