MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter
February 1984
Revised October 1999
MM74HC4049 • MM74HC4050
Hex Inverting Logic Level Down Converter •
Hex Logic Level Down Converter
General Description
The MM74HC4049 and the MM74HC4050 utilize
advanced silicon-gate CMOS technology, and have a mod-
ified input protection structure that enables these parts to
be used as logic level translators which will convert high
level logic to a low level logic while operating from the low
logic supply. For example, 0–15V CMOS logic can be con-
verted to 0–5V logic when using a 5V supply. The modified
input protection has no diode connected to V
CC
, thus allow-
ing the input voltage to exceed the supply. The lower zener
diode protects the input from both positive and negative
static voltages. In addition each part can be used as a sim-
ple buffer or inverter without level translation. The
MM74HC4049 is pin and functionally compatible to the
CD4049BC and the MM74HC4050 is compatible to the
CD4050BC
Features
s
Typical propagation delay: 8 ns
s
Wide power supply range: 2V–6V
s
Low quiescent supply current: 20
µA
maximum (74HC)
s
Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
MM74HC4049M
MM74HC4049SJ
MM74HC4049MTC
MM74HC4049N
MM74HC4050M
MM74HC4050SJ
MM74HC4050MTC
MM74HC4050N
Package Number Package Description
M16A
M16D
MTC16
N16E
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
MM74HC4049
MM74HC4050
© 1999 Fairchild Semiconductor Corporation
DS005214
www.fairchildsemi.com
MM74HC4049 • MM74HC4050
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
ZK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260°C
600 mW
500 mW
−0.5
to
+7.0V
−1.5
to
+18V
−0.5
to V
CC
+0.5V
−20
mA
±25
mA
±50
mA
−65°C
to
+150°C
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input Voltage
(V
IN
)
DC Output Voltage
(V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
−40
+85
°C
0
V
CC
V
2
0
Max
6
15
Units
V
V
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level Input
Voltage
V
IL
Maximum LOW Level Input
Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
Conditions
(Note 4)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
T
A
=
25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
±0.5
2.0
T
A
= −40°C
to 85°C T
A
= −55°C
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
±5
20
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
±5
40
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
Units
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4 mA
|I
OUT
|
≤
5.2 mA
I
IN
I
CC
Maximum Input Current
V
IN
=
V
CC
or GND
V
IN
=
15V
Maximum Quiescent Supply V
IN
=
V
CC
or GND
Current
I
OUT
=
0
µA
4.5V
6.0V
6.0V
2.0V
6.0V
4.5V
6.0V
Note 4:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
MM74HC4049 • MM74HC4050
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
Symbol
t
PHL
, t
PLH
Parameter
Maximum Propagation Delay
Conditions
Typ
8
Guaranteed
Limit
15
Units
ns
AC Electrical Characteristics
V
CC
=
2.0V to 6.0V, C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
t
PHL
, t
PLH
Parameter
Maximum Propagation
Delay
t
THL
, t
TLH
Maximum Output
Rise and Fall
Time
C
PD
C
IN
Power Dissipation
Capacitance (Note 5)
Maximum Input
Capacitance
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
Conditions
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
T
A
=
25°C
Typ
30
10
9
25
7
6
25
5
10
85
17
15
75
15
13
T
A
= −40°
to 85°C T
A
= −55°
to 125°C
Guaranteed Limits
100
20
18
95
19
16
130
26
22
110
22
19
Units
ns
ns
ns
ns
ns
ns
pF
(per gate)
10
10
pF
3
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Analogue and Mixed Signal
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