www.murata-ps.com
ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
PRODUCT OVERVIEW
The ADC-208A utilizes an advanced VLSI 1.2
micron CMOS in providing 20MHz sampling rates
at 8-bits. The flexibility of the design architecture
and process delivers latch-up free operation
without external components and operation over
the full military range.
The ADC-208A is mechanically and electri-
cally equivalent to the ADC-208 Series, with the
exception of the OVERFLOW (pin 13) and ENABLE
(pins 11 and 12) functions. These functions are not
offered on the ADC-208A.
FEATURES
■
■
■
■
■
■
■
■
■
■
Pin
1
2
3
4
5
6
7
8
9
10
11
12
8-bit flash A/D converter
20MHz sampling rate
10MHz full-power bandwidth
Sample-hold not required
Low power CMOS
+5Vdc operation
1.2 Micron CMOS
8-Bit latched outputs
Surface-mount version
No missing codes
INPUT/OUTPUT CONNECTIONS
FUNCTION
Pin
24
VDD
CLOCK INPUT
–REFERENCE
ANA/DIG GND (VSS)
ANALOG INPUT
REF MIDPOINT
ANALOG INPUT
ANA/DIG GND (VSS)
+REFERENCE
VDD
N.C.
N.C.
23
22
21
20
19
18
17
16
15
14
13
FUNCTION
BIT 8 (LSB)
BIT 7
BIT 6
BIT 5
REF 1/4 FS
VDD
REF 3/4 FS
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
N.C.
02
01
ANALOG INPUT
02
01
CLOCK
GENERATOR
2
CLOCK
5,7
R2
+REFERENCE
9
D
R
G
1Ω
Q
D
G
Q
14
BIT 1
D
G
Q
D
G
D
G
R2
Q
256 to
7 ENCODER
D
G
Q
15
BIT 2
¾ REFERENCE
18
D
G
R
Q
16
BIT 3
1Ω R2
MIDPOINT
REFERENCE
6
Q
17
BIT 4
1Ω
¼ REFERENCE
20
R2
D
G
D
G
R
R2
Q
D
G
Q
Q
21
BIT 5
22
BIT 6
– REFERENCE
3
D
D
G
Q
G
DIGITAL GND
Q
PINS 1, 10, 19 +5V
+V
DD
23
BIT 7
24
PINS 4-8
ANALOG GND
BIT 8
(LSB)
For full details go to
www.murata-ps.com/rohs
Figure 1. ADC-208A Block Diagram
www.murata-ps.com
Technical enquiries
email: data.acquisition@murata-ps.com, tel:
+1 508 339 3000
MDA_ADC-208A.B01
Page 1 of 4
ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Power Supply Voltage (V
DD
Pin 1, 10, 19)
Digital Inputs
Analog Input
Reference Inputs
Digital Outputs
(short circuit protected to ground)
Lead Temperature (10 sec. max.)
Storage Temperature
PERFORMANCE
UNITS
Volts
Volts
Volts
Volts
Volts
°C
°C
Int. Linearity @ +25°C
(ref. unadjusted)
End-point
Best-fit Line
Int. Linearity Over Temp.
(ref. unadjusted)
End-point
Best-fit Line
Zero-Scale Offset
(Code "0" to "1" transition)
Gain Error
Differential Gain
➂
Differential Phase
➂
degrees
Aperture Delay
Aperture Jitter
Harmonic Distortion
(8MHz second order harm.)
Ref. bandwidth
(See tech note 5)
Power Supply Rejection
No Missing Codes
Power Supply Range (+V
DD
)
Power Supply Current
+25°C
+125°C
–55°C
Power Dissipation
+25°C
+125°C
–55°C
Operating Temp. Range, Case:
MC/LM Versions
MM/LM/QL Versions
Storage Temp. Range
Package Type
DIP
LCC
MIN.
TYP.
MAX.
UNITS
LIMITS
–0.5 to +7
–0.5 to +5.5
–0.5 to (+V
DD
+0.5)
–0.5 to (+V
DD
+0.5)
–0.5 to +5.5
+300 max.
–65 to +150
—
—
±2
±1.6
±2.6
±1.9
LSB
LSB
—
—
—
—
—
—
—
—
–40
±2.3
±1.8
±1
±1.5
2
1.1
8
50
–46
±2.6
±2.0
±2
±3
—
—
—
—
—
LSB
LSB
LSB
LSB
%
FUNCTIONAL SPECIFICATIONS
(Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V,
–REFERENCE = ground, unless noted)
ANALOG INPUT
Single-Ended, Non-Isolated
Input Range DC - 20MHz
Analog Input Capacitance
(static - Pin 5 to 7)
(dynamic - Pin 5 to 7)
Reference Ladder Resistance
Reference Input (Note 5)
Logic Levels
Logic "1"
Logic "0"
Logic Loading
Logic Loading "1"
Logic Loading "0"
Clock Low Pulse Width
Logic Levels
Logic "1"
Logic "0"
Logic Loading
Logic Loading "1"
Logic Loading "0"
Output Data Valid Delay From
Rising Clock Edge
99% probability
100% probability
+25°C
–55°C to +125°C
Data Output Resolution
Data Coding
Sampling Rate
➁
Full Power Bandwidth
Diff. Linearity @ +25°C
(See tech note 7)
Code Transitions
Center of Codes
Diff. Linearity Over Temp.
Code Transitions
Center of Codes
Int. Linearity @ +25°C
(See tech note 4)(ref. adjusted)
End-point
Best-fit Line
Int. Linearity Over Temp.
(ref. adjusted)
Best-fit Line
MIN.
0
–
–
–
–0.5
TYP.
–
20
64
500
–
MAX.
+5.0
–
–
–
V
DD
+0.5
UNITS
Volts
pF
pF
Ohms
Volts
ns
ps
dB
—
10
—
MHz
—
±0.02
±0.05 %FSR/%Vs
Over the operating temperature range
POWER REQUIREMENTS
+3.0
—
—
—
—
—
—
+5.0
+45
+40
+50
225
200
250
+5.5
+65
+60
+70
325
300
350
Volts
mA
mA
mA
mW
mW
mW
DIGITAL INPUTS
3.2
—
—
—
15
—
—
+1
+1
25
—
0.8
+5
+5
—
Volts
Volts
µA
µA
nSec
DIGITAL OUTPUTS
2.4
—
4
4
4.5
—
—
—
5.0
0.4
—
—
Volts
Volts
mA
mA
PHYSiCAL ENVIRONMENTAL
0
–55
–65
—
—
—
+70
+125
+150
°C
°C
°C
24-pin ceramic DIP
24-pin ceramic LCC
5
5
—
8
10
15
nSec
nSec
nSec
Bits
10
25
—
40
—
—
Straight binary
20
—
—
—
Footnotes:
➀
Maximum input impedance is a function of clock frequency.
➁
At full-power input.
➂
For 10-step, 40 IRE NTSC ramp test.
PERFORMANCE
15
10
MSPS
MHz
TECHNICAL NOTES
1. The Reference ladder is floating with respect to VDD and may be referenced anywhere
within the specified limits. AC modulation of the reference voltage may also be utilized; contact
DATEL for further information.
2. Clock Pulse Width – To improve performance when input signals may exceed Nyquist
bandwidths, the clock duty cycle can be adjusted so that the low portion (sample mode) of
the clock pulse is 15nSec wide. Reducing the sampling time period minimizes the amount the
input voltage slews and prevents the comparators from saturating.
3. A full-scale input produces all "1" on the data outputs.
4. DATEL uses the conservative definitions when specifying Intergal Linearity (end-point) and
Differential Linearity (code transition). The specifications using the less conservative definition
have also been provided as a comparative specification for products specified this way.
5. The process that is used to fabricate the ADC-208A eliminates the latchup phenomena
that has plagued CMOS devices in the past. These converters do not require external protec-
tion diodes.
6. For clock rates less than 100kHz, there may be some degradation in offset and differential
nonlinearity. Performance may be improved by increasing the clock duty cycle (decreasing
the time spent in the sample mode).
—
—
—
—
±0.5
±0.25
±0.5
±0.25
±1.0
—
±1.0
—
LSB
LSB
LSB
LSB
—
—
—
—
±1/2
±1/2
LSB
LSB
—
±1/2
±1
LSB
www.murata-ps.com
Technical enquiries
email: sales@murata-ps.com, tel:
+1 508 339 3000
MDA_ADC-208A.B01
Page 2 of 4
ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
7. Connect the converter appropriately; a typical connection circuit is shown in Figure 2.
Then apply an appropriate clock input.The reference input should be held to ±0.1% accuracy
or better. Do not use the +5V power supply as a reference without precision regulation and
high-frequency decoupling capacitors.
8. Zero Adjustment - Adjusting the voltage at –REFERENCE (pin 3) adjusts the offset or
zero of the device. Pin 3 can be tied to GROUND for operation without adjustments
9. Full Scale Adjustment - Adjusting the voltage at +REFERENCE (pin 9) adjusts the gain of
the device. Pin 9 can be tied directly to a +5V reference for operation without adjustment.
10. Integral Nonlinearity Adjustments - Provision is made for optional adjustment of Integral
Nonlinearity through access of the reference's ¼, ½, and ¾ full scale points. For example, the
REF. MIDPOINT (pin 6) can be tied to a precision voltage halfway between +REFERENCE
and –REFERENCE. Pins 6, 18 and 20 should be bypassed to GROUND through 0.1µF
capacitors for operation without INL adjustments
Table 1. ADC-208A Output Code
ANALOG
INPUT
0.00V
+0.02V
+1.28V
+2.54V
+2.56V
+2.58V
+3.84V
+5.10V
CODE
Zero 0000
+1 LSB
+¼ FS
+½ FS-ILSB
+½ FS
+½ FS+ILSB
+¾ FS
+FS
DATA
1234
0000
0000
0100
0111
1000
1000
1100
1111
DATA 5678
0000
0001
0000
1111
0000
0001
0000
1111
DECIMAL
0
1
64
127
128
129
192
255
HEX
00
01
40
7F
80
81
C0
FF
Note:
Values shown here are for a +5.12Vdc reference. Scale other refereces proportion-
ally. (+REF=+5.12V, –REF=GND, ¼, ½, and ¾ References FS=No Connection)
+5V
4.7μF
+
+15
0.01μF
+5V
D GND 4
A GND 8
VDD 1,10,19
0.1μF
+
4.7μF
B8
B7
B6
B5
B4
B3
B2
B1
24 (LSB)
23
22
21
17
16
15
14 (MSB)
20
12
5
HA-5033
10
11
10Ω
20MHz CLOCK
CLOCK 2
VIN 5,7
REF-3
–15
+
+15V
2
2
6
LM324
REF. D2
4
4.7μF
2kΩ
3
5
10kΩ
1+N
+
1-N
1
+15V
REF+9
4.7μF
0.1μF
REF MID 6
HP2811
R¼
R¾
18
9
0.1μF
1-N
8
LM324
+
1+N
4.7μF
0.1μF
10
1kΩ
0.1μF
1.5kΩ
6
1-N
7
1kΩ
0.1μF
1.5kΩ
12
1kΩ
13
0.1μF
2kΩ
1+N
4.7μF
1-N
14
LM324
+
0.1μF
LM324
5
1+N
4.7μF
+
0.1μF
Figure 2. ADC-208A Typical Connection Diagram
www.murata-ps.com
Technical enquiries
email: sales@murata-ps.com, tel:
+1 508 339 3000
MDA_ADC-208A.B01
Page 3 of 4
ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
MECHNICAL DIMENSIONS
ADC-208A DIP
1.250
(31.7)
0.050
(1.27)
Pin 9
ADC-208A LCC
0.250 ±0.005
(6.35)
DATEL
ADC-208A
0.500
(12.7)
0.610
(15.5)
Pin 21
0.400 SQ.
+0.010, –0.005
(10.16)
PIN 1
IDENTIFIER
Pin 1
0.020 ±0.005
(0.50)
0.190
(4.9)
0.38
(9.7)
0.090 Max.
(2.28)
0.190
(4.9)
0.050
(1.3)
0.020
(0.5)
0.100
(2.5)
AUTO ZERO
SAMPLE
N
02
AUTO ZERO
SAMPLE
N+1
02
AUTO ZERO
SAMPLE
N+2
02
ORDERING INFORMATION
MODEL
ADC-208AMC
TEMP. RANGE
0°C to +70°C
–55°C to +125°C
➀
0°C to +70°C
–55°C to +125°C
➁
PACKAGE
24-pin DIP
24-pin DIP
24-pin LCC
24-pin LCC
01
01
01
N DATA
N+1 DATA
ADC-208AMM
ADC-208ALC
40nSec max.
40nSec max.
ADC-208ALM
Figure 3 Timing Diagram
➀
The ADC-208AMM-QL replaces the ADC-208MM-QL and includes DATEL
QL High-Reliability Screening.
➁
The ADC-208ALM-QL replaces the ADC-208LM.
USA:
Canada:
UK:
France:
Germany:
Japan:
China:
Singapore:
Mansfield (MA), Tel: (508) 339-3000, email: sales@murata-ps.com
Toronto, Tel: (866) 740-1232, email: toronto@murata-ps.com
Milton Keynes, Tel: +44 (0)1908 615232, email: mk@murata-ps.com
Montigny Le Bretonneux, Tel: +33 (0)1 34 60 01 01, email: france@murata-ps.com
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Shanghai, Tel: +86 215 027 3678, email: shanghai@murata-ps.com
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Parkway Centre, Tel: +65 6348 9096, email: singapore@murata-ps.com
Technical enquiries
email: sales@murata-ps.com, tel:
+1 508 339 3000
Murata Power Solutions, Inc.
11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A.
Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
www.murata-ps.com email: sales@murata-ps.com ISO 9001 and 14001 REGISTERED
03/20/09
Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other
technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply
the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without
notice.
© 2008 Murata Power Solutions, Inc.
www.murata-ps.com
MDA_ADC-208A.B01
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