Commercial (FS6377-01) and industrial (FS6377-01i)
temperature ranges
2
The FS6377 is a CMOS clock generator IC designed to
minimize cost and component count in a variety of elec-
2
tronic systems. Three I C-programmable phase-locked
loops feeding four programmable muxes and post divid-
ers provide a high degree of flexibility.
Figure 1: Pin Configuration
SDA
SEL_CD
PD
VSS
XIN
XOUT
OE
VDD
1
2
3
16
15
14
SCL
CLK_A
VDD
CLK_B
CLK_C
VSS
CLK_D
ADDR
FS6377
4
5
6
7
8
13
12
11
10
9
16-pin (0.150”) SOIC
Figure 2: Block Diagram
XIN
XOUT
Reference
Oscillator
PLL A
Mux A
Post
Divider A
CLK_A
PD
Power Down
Control
PLL B
Mux B
Post
Divider B
CLK_B
SCL
SDA
ADDR
I
2
C-bus
Interface
PLL C
Mux C
Post
Divider C
CLK_C
SEL_CD
Mux D
Post
Divider D
CLK_D
OE
FS6377
I
2
C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc., reserves the right to change the detail specifications as may be required to permit improvements in the design of
its products.
6.5.03
FS6377-01
Programmable 3-PLL Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TYPE
DI
U
O
DI
DI
U
U
NAME
SDA
SEL_CD
PD
VSS
XIN
XOUT
OE
VDD
ADDR
CLK_D
VSS
CLK_C
CLK_B
VDD
CLK_A
SCL
Serial Interface Data Input/Output
DESCRIPTION
Selects one of two PLL C, Mux C/D, and Post Divider C/D combinations
Power-Down Input
Ground
Crystal Oscillator Input
Crystal Oscillator Output
Output Enable Input
Power Supply (5V to 3.3V)
Address Select
D Clock Output
Ground
C Clock Output
B Clock Output
Power Supply (5V to 3.3V)
A Clock Output
Serial Interface Clock Input
P
AI
AO
DI
U
P
DI
U
DO
P
DO
DO
P
DO
DI
U
3.0
3.1
Functional Block Description
Phase Locked Loops
Figure 3: PLL Diagram
LFTC
Each of the three on-chip phase-locked loops (PLLs) is a
standard phase- and frequency-locked loop architecture
that multiplies a reference frequency to a desired fre-
quency by a ratio of integers. This frequency multiplica-
tion is exact.
As shown in Figure 3, each PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal loop filter, a Voltage-Controlled Oscil-
lator (VCO), and a Feedback Divider.
During operation, the reference frequency (f
REF
), gener-
ated by the on-board crystal oscillator, is first reduced by
the Reference Divider. The divider value is called the
“modulus,” and is denoted as N
R
for the Reference Di-
vider. The divided reference is then fed into the PFD.
The PFD controls the frequency of the VCO (f
VCO
)
through the charge pump and loop filter. The VCO pro-
vides a high-speed, low noise, continuously variable fre-
quency clock source for the PLL. The output of the VCO
is fed back to the PFD through the Feedback Divider (the
modulus is denoted by N
F
) to close the loop.
2
REFDIV[7:0]
CP
Loop
Filter
f
REF
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
f
PD
UP
Charge
Pump
DOWN
FBKDIV[10:0]
Voltage
Controlled
Oscillator
f
VCO
Feedback
Divider
(N
F
)
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
frequency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference fre-
quency and the VCO frequency is
æ
N
f
VCO
=
f
REF
ç
F
ç
N
è
R
ö
÷
.
÷
ø
6.5.03
FS6377-01
Programmable 3-PLL Clock Generator IC
To understand the operation, refer to Figure 4. The M-
counter (with a modulus always equal to M) is cascaded
with the dual-modulus prescaler. The A-counter controls
the modulus of the prescaler. If the value programmed
into the A-counter is A, the prescaler will be set to divide
by N+1 for A prescaler outputs. Thereafter, the prescaler
divides by N until the M-counter output resets the A-
counter, and the cycle begins again. Note that N=8, and
A and M are binary numbers.
Suppose that the A-counter is programmed to zero. The
modulus of the prescaler will always be fixed at N; and
the entire modulus of the feedback divider becomes M
×
N.
Next, suppose that the A-counter is programmed to a
one. This causes the prescaler to switch to a divide-by-
N+1 for its first divide cycle and then revert to a divide-by-
N. In effect, the A-counter absorbs (or “swallows”) one
extra clock during the entire cycle of the Feedback Di-
vider. The overall modulus is now seen to be equal to
M
×
N+1.
This example can be extended to show that the Feed-
back Divider Modulus is equal to M
×
N+A, where A≤M.
3.1.3 Feedback Divider Programming
For proper operation of the Feedback Divider, the A-
counter must be programmed only for values that are
less than or equal to the M-counter. Therefore, not all
divider moduli below 56 are available for use. The selec-
tion of divider values is listed in Table 2.
Above a modulus of 56, the Feedback Divider can be
programmed to any value up to 2047.
3.1.1 Reference Divider
The Reference Divider is designed for low phase jitter.
The divider accepts the output of the reference oscillator
and provides a divided-down frequency to the PFD. The
Reference Divider is an 8-bit divider, and can be pro-
grammed for any modulus from 1 to 255 by programming
the equivalent binary value. A divide-by-256 can also be
achieved by programming the eight bits to 00h.
3.1.2 Feedback Divider
The Feedback Divider is based on a dual-modulus
prescaler technique. The technique allows the same
granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at
low speed. A high-speed pre-divider (also called a
prescaler) is placed between the VCO and the program-
mable Feedback Divider because of the high speeds at
which the VCO can operate. The dual-modulus technique
insures reliable operation at any speed that the VCO can
achieve and reduces the overall power consumption of
the divider.
For example, a fixed divide-by-eight could be used in the
Feedback Divider. Unfortunately, a divide-by-eight would
limit the effective modulus of the entire feedback divider
to multiples of eight. This limitation would restrict the abil-
ity of the PLL to achieve a desired input-frequency-to-
output-frequency ratio without making both the Reference
and Feedback Divider values comparatively large.
A large feedback modulus means that the divided VCO
frequency is relatively low, requiring a wide loop band-
width to permit the low frequencies. A narrow loop band-
width tuned to high frequencies is essential to minimizing
jitter; therefore, divider moduli should always be as small
as possible.
Table 2: Feedback Divider Modulus Under 56
M-COUNTER:
FBKDIV[10:3]
00000001
00000010
00000011
00000100
00000101
00000110
00000111
A-COUNTER: FBKDIV[2:0]
000
8
16
24
32
40
48
56
001
9
17
25
33
41
49
57
010
-
18
26
34
42
50
58
011
-
-
27
35
43
51
59
100
-
-
-
36
44
52
60
101
-
-
-
-
45
53
61
110
-
-
-
-
-
54
62
111
-
-
-
-
-
-
63
Figure 4: Feedback Divider
f
VCO
Dual
Modulus
Prescaler
FBKDIV[2:0]
M
Counter
f
PD
FBKDIV[10:3]
A
Counter
FEEDBACK DIVIDER MODULUS
6.5.03
3
FS6377-01
Programmable 3-PLL Clock Generator IC
3.2
Post Divider Muxes
4.1
SEL_CD Input
As shown in Figure 2, an input mux in front of each Post
Divider stage can select from any one of the PLL fre-
quencies or the reference frequency. The frequency se-
2
lection is done via the I C-bus.
The input frequency on two of the four muxes (Mux C and
D in Figure 2) can be changed without reprogramming by
a logic-level input on the SEL_CD pin.
3.3
Post Dividers
The Post Divider performs several useful functions. First,
it allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it
changes the basic PLL equation to
The SEL_CD pin provides a way to alter the operation of
PLL C, Muxes C and D, and Post Dividers C and D with-
out having to reprogram the device. A logic-low on the
SEL_CD pin selects the control bits with a “C1” or “D1”
notation, per Table 3. A logic-high on the SEL_CD pin
selects the control bits with “C2” or “D2” notation, per
Table 3.
Note that changing between two running frequencies us-
ing the SEL_CD pin may produce glitches in the output,
especially if the post-divider(s) is/are altered.
4.2
Power-Down and Output Enable
æ
N
f
CLK
=
f
REF
ç
F
ç
N
è
R
öæ
1
֍
֍
N
øè
P
ö
÷
÷
ø
where N
F
, N
R
, and N
P
are the Feedback, Reference, and
Post Divider moduli respectively, and f
CLK
and f
REF
are the
output and reference oscillator frequencies. The extra
integer in the denominator permits more flexibility in the
programming of the loop for many applications where
frequencies must be achieved exactly.
The modulus on two of the four Post Dividers muxes
(Post Dividers C and D in Figure 2) can be altered with-
out reprogramming by a logic level on the SEL_CD pin.
A logic-high on the PD pin powers down only those por-
tions of the FS6377 which have their respective power-
down control bits enabled. Note that the PD pin has an
internal pull-up.
When a Post Divider is powered down, the associated
output driver is forced low. When all PLLs and Post Di-
viders are powered down the crystal oscillator is also
powered down. The XIN pin is forced low, and the XOUT
pin is pulled high.
A logic-low on the OE pin tristates all output clocks. Note
that this pin has an internal pull-up.
4.3
Oscillator Overdrive
4.0
Device Operation
The FS6377 powers up with all internal registers cleared
to zero, delivering the crystal frequency to all outputs. For
operation to occur, the registers must be loaded in a
most-significant-bit (MSB) to least-significant-bit (LSB)
order. The register mapping of the FS6377 is shown in
2
Table 3, and I C-bus programming information is detailed
in Section 5.0.
Control of the Reference, Feedback, and Post Dividers is
detailed in Table 6. Selection of these dividers directly
controls how fast the VCO will run. The maximum VCO
speed is noted in Table 15.
For applications where an external reference clock is
provided (and the crystal oscillator is not required), the
reference clock should be connected to XOUT and XIN
should be left unconnected (float).
For best results, make sure the reference clock signal is
as jitter-free as possible, can drive a 40pF load with fast
rise and fall times, and can swing rail-to-rail.
If the reference clock is not a rail-to-rail signal, the refer-
ence must be AC coupled to XOUT through a 0.01µF or
0.1µF capacitor. A minimum 1V peak-to-peak signal is
required to drive the internal differential oscillator buffer.
6.5.03
4
FS6377-01
Programmable 3-PLL Clock Generator IC
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the de-
vice after the first sixteen bytes will overflow into the first
register, then the second, and so on, in a first-in, first-
overwritten fashion.
5.1.5 Acknowledge
When addressed, the receiving device is required to gen-
erate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to co-
incide with the Acknowledge bit. The acknowledging de-
vice must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The master must signal an end of data to the slave by not
generating and acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to enable the master
to generate a STOP condition.
5.0
I C-bus Control Interface
2
This device is a read/write slave device
2
meeting all Philips I C-bus specifications
except a “general call.” The bus has to be
controlled by a master device that generates
the serial clock SCL, controls bus access, and generates
the START and STOP conditions while the device works
as a slave. Both master and slave can operate as a
transmitter or receiver, but the master device determines
which mode is activated. A device that sends data onto
the bus is defined as the transmitter, and a device re-
ceiving data as the receiver.
2
I C-bus logic levels noted herein are based on a percent-
age of the power supply (V
DD
). A logic-one corresponds
to a nominal voltage of V
DD
, while a logic-zero corre-
sponds to ground (V
SS
).
5.1
Bus Conditions
Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line while the clock line is
high will be interpreted by the device as a START or
STOP condition. The following bus conditions are defined
2
by the I C-bus protocol.
5.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
5.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL in-
put is high indicates a START condition. All commands to
the device must be preceded by a START condition.
5.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
5.1.4 Data Valid
The state of the SDA line represents valid data if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
5.2
I
2
C-bus Operation
All programmable registers can be accessed randomly or
sequentially via this bi-directional two wire digital inter-
2
face. The device accepts the following I C-bus com-
mands.
5.2.1 Slave Address
After generating a START condition, the bus master
broadcasts a seven-bit slave address followed by a R/W
bit.
The address of the device is:
A6
1
A5
0
A4
1
A3
1
A2
X
A1
0
A0
0
where X is controlled by the logic level at the ADDR pin.
The variable ADDR bit allows two different devices to
2
exist on the same bus. Note that every device on an I C-
bus must have a unique address to avoid bus conflicts.
The default address sets A2 to one via the pull-up on the
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