Jitter Cleaner and Clock Generator with
6 Differential or 13 LVCMOS Outputs
Data Sheet
FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <±150 ps
6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
6 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ½ period of VCO
output divider
Output-to-output skew: <±50 ps
Duty-cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <200 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Distribution phase noise floor: −160 dBc/Hz
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I²C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate up to 130 MHz
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate of up to 259 MHz
Integrated low noise VCO
OSC
REFA,
REFA
REFB,
REFB
REF_TEST
PLL1
PLL2
AD9524
FUNCTIONAL BLOCK DIAGRAM
AD9524
OUT0,
OUT0
OUT1,
OUT1
SCLK/SCL
SDIO/SDA
SDO
CONTROL
INTERFACE
(SPI AND I
2
C)
ZERO
DELAY
EEPROM
6-CLOCK
DISTRIBUTION
OUT4,
OUT4
OUT5,
OUT5
ZD_IN, ZD_IN
Figure 1.
GENERAL DESCRIPTION
The
AD9524
provides a low power, multi-output, clock
distribution function with low jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to
4.0 GHz.
The
AD9524
is defined to support the clock requirements for
long term evolution (LTE) and multicarrier GSM base station
designs. It relies on an external VCXO to provide the reference
jitter cleanup to achieve the restrictive low phase noise require-
ments necessary for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates six low noise outputs with a range of 1 MHz to 1 GHz,
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free coarse timing adjustment in
increments that are equal to one-half the period of the signal
coming out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user defined register settings for power-up and
chip reset.
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
Rev. F
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09081-001
AD9524* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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REFERENCE MATERIALS
Product Selection Guide
•
RF Source Booklet
Technical Articles
•
Dual-Loop Clock Generator Cleans Jitter, Provides
Multiple High-Frequency Outputs
EVALUATION KITS
•
AD9524 Evaluation Board
DOCUMENTATION
Application Notes
•
AN-1066: Power Supply Considerations for AD9523,
AD9524, and AD9523-1 Low Noise Clocks
Data Sheet
•
AD9524: Jitter Cleaner and Clock Generator with 6
Differential or 13 LVCMOS Outputs Data Sheet
User Guides
•
UG-169: Evaluating the AD9523/AD9524 Clock Generator
DESIGN RESOURCES
•
AD9524 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DISCUSSIONS
View all AD9524 EngineerZone Discussions.
TOOLS AND SIMULATIONS
•
ADIsimCLK Design and Evaluation Software
•
AD9524 IBIS Model
SAMPLE AND BUY
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TECHNICAL SUPPORT
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AD9524
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Conditions ..................................................................................... 4
Supply Current .............................................................................. 4
Power Dissipation ......................................................................... 6
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, and ZD_IN,
ZD_IN Input Characteristics ...................................................... 6
OSC_CTRL Output Characteristics .......................................... 7
REF_TEST Input Characteristics ............................................... 7
PLL1 Characteristics .................................................................... 7
PLL1 Output Characteristics ...................................................... 7
Distribution Output Characteristics (OUT0, OUT0 to OUT5,
OUT5) ............................................................................................ 8
Timing Alignment Characteristics ............................................ 9
Jitter and Noise Characteristics .................................................. 9
PLL2 Characteristics .................................................................... 9
Logic Input Pins—PD, SYNC, RESET, EEPROM_SEL,
REF_SEL ...................................................................................... 10
Status Output Pins—STATUS1, STATUS0 ............................. 10
Serial Control Port—SPI Mode ................................................ 10
Serial Control Port—I²C Mode ................................................ 11
Absolute Maximum Ratings .......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution ................................................................................ 12
Pin Configuration and Function Descriptions ........................... 13
Typical Performance Characteristics ........................................... 15
Input/Output Termination Recommendations .......................... 17
Data Sheet
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
Detailed Block Diagram ............................................................ 19
Overview ..................................................................................... 19
Component Blocks—Input PLL (PLL1).................................. 20
Component Blocks—Output PLL (PLL2) .............................. 21
Clock Distribution ..................................................................... 23
Zero Delay Operation ................................................................ 25
Lock Detect ................................................................................. 25
Reset Modes ................................................................................ 26
Power-Down Mode .................................................................... 26
Serial Control Port ......................................................................... 27
SPI/I²C Port Selection................................................................ 27
I²C Serial Port Operation .......................................................... 27
SPI Serial Port Operation .......................................................... 30
SPI Instruction Word (16 Bits) ................................................. 31
SPI MSB/LSB First Transfers .................................................... 31
EEPROM Operations ..................................................................... 34
Writing to the EEPROM ........................................................... 34
Reading from the EEPROM ..................................................... 34
Programming the EEPROM Buffer Segment ......................... 35
Power Dissipation and Thermal Considerations ....................... 37
Clock Speed and Driver Mode ................................................. 37
Evaluation of Operating Conditions........................................ 37
Thermally Enhanced Package Mounting Guidelines ............ 38
Control Registers ............................................................................ 39
Control Register Map ................................................................ 39
Control Register Map Bit Descriptions ................................... 43
Outline Dimensions ....................................................................... 56
Ordering Guide .......................................................................... 56
Rev. F | Page 2 of 56
Data Sheet
REVISION HISTORY
9/15—Rev. E to Rev. F
Changes to Features Section ............................................................ 1
Changes to Table 7 ............................................................................ 7
Changes to Table 12 .......................................................................... 9
Changes to Table 40 ........................................................................44
Changes to Table 47 ........................................................................47
1/14—Rev. D to Rev. E
Change Pin 34 from VDD1.8_OUT[0:3] to VDD1.8_OUT[2:3]
and Pin 42 from NC to VDD1.8_OUT[0:1] ................................13
Changes to Writing to the EEPROM Section.................................34
Added Register 0x190 .....................................................................40
Changes to EEPROM Buffer Registers .........................................41
Added Table 51 ................................................................................50
2/13—Rev. C to Rev. D
Deleted VDD1.8_PLL2................................................. Throughout
Changes to Data Sheet Title ............................................................ 1
Added T
J
of 115°C, Table 1 .............................................................. 4
Changed VDD3_PLL1, Supply Voltage for PLL1 Typical
Parameter from 22 mA to 37 mA and Changed VDD3_PLL1,
Supply Voltage for PLL1 Maximum Parameter from 25.2 mA to
43 mA, Table 2 ................................................................................... 4
Changes to Table 3 ............................................................................ 6
Added PLL1 Characteristics Section and Table 7, Renumbered
Sequentially ........................................................................................ 7
Changes to Table 9 Summary Statement and Changed Differen-
tial Output Voltage Magnitude Unit from mV to V, Table 9 ........... 8
Changed Output Timing Skew Between LVPECL, HSTL, and
LVDS Outputs from 164 ps to 234 ps; Added Endnote 1;
Table 10 ............................................................................................... 9
Changes to Pin 5 Description, Table 19 .......................................13
Changed Pin 42 from VDD1.8_PLL2 to NC, Table 19 ..............14
Changes to Figure 24 ......................................................................21
Changes to Multimode Output Drivers Section .........................24
Changes to Clock Distribution Synchronization Section ..........25
Changes to Figure 29 and Added Lock Detect Section...............26
Added Reset Modes Section and Power-Down Mode Section .... 27
Changes to Pin Descriptions Section and Read Section ............31
Added Figure 38; Renumbered Sequentially ...............................33
Changes to Register Section Definition Group Section .............36
Changes to Power Dissipation and Thermal Considerations
Section ..............................................................................................38
Changes to Table 31 ........................................................................40
Change to Bit 4 and Bits[1:0] Description, Table 40...................45
Changes to Bit 2 Description, Table 41 and Bits[7:6]
Description, Table 42 ......................................................................46
Changes to Bits[1:0] Description, Table 43..................................47
AD9524
Changes to Bit 4, Bits [3:2] Descriptions, Table 47 ..................... 48
Changes to Bit 3 Descriptions Table 48 ........................................ 49
Changed Bit 6 Name from Status PLL2 Feedback Clock to Status
PLL1 Feedback Clock, Table 54 ...................................................... 52
3/11—Rev. A to Rev. B
Added Table Summary, Table 8 ....................................................... 7
Changes to Table 9 ............................................................................ 8
Changes to EEPROM Operations Section and Writing to the
EEPROM Section ............................................................................ 32
Changes to Addr (Hex) 0x01A, Bits[4:3], Table 30 .................... 37
Changes to Bits[4:3], Table 40 ....................................................... 43
1/11—Rev. 0 to Rev. A
Changes to General Description Section ....................................... 1
Changes to Specifications Summary Statement ............................ 4
Changes to Test Conditions/Comments for VDD3_PLL1,
Supply Voltage for PLL1 Parameter, Table 2.................................. 4
Changes to Typical Configuration and Low Power Typical
Configuration Parameters, Table 3 ................................................. 5
Changes to Input High Voltage and Input Low Voltage
Parameters; Added Input Threshold Voltage Parameter,
Table 4 ................................................................................................. 5
Changed Differential Output Voltage Swing Parameters to
Differential Output Voltage Magnitude; Changes to Test
Conditions/Comments, Table 8 ...................................................... 7
Changed Junction Temperature Parameter from 150°C to
115°C, Table 16 ................................................................................ 11
Added Figure 14; Renumbered Sequentially ............................... 15
Changes to Figure 15, Figure 17, and Figure 19; Change to
Caption of Figure 21 ....................................................................... 16
Added PLL1 Lock Detect Section ................................................. 19
Changes to VCO Calibration Section........................................... 21
Changed Output Mode Section to Multimode Output
Drivers; Changes to Multimode Output Drivers Section .......... 22
Changes to Figure 29 ...................................................................... 24
Changes to SPI/I2C Port Selection Section ................................. 25
Change to SPI Instruction Word (16 Bits) Section ..................... 29
Added Power Dissipation and Thermal Considerations
Section .............................................................................................. 35
Changes to Table 34 to Table 36 and Table 38 ............................. 42
Change to Register 0x0F3, Bit 1 Description, Table 47 .............. 45
Change to Register 0x198, Bits[7:2], Table 50 ............................. 47
Changes to Table 52 ........................................................................ 48
Changes to Register 0x230 and Register 0x231, Table 54 .......... 49
7/10—Revision 0: Initial Version
Rev. F | Page 3 of 56
AD9524
SPECIFICATIONS
Data Sheet
f
VCXO
= 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, f
VCO
= 3932.16 MHz, doubler is off, channel control
low power mode off, divider phase =1, unless otherwise noted. Typical is given for VDD = 3.3 V ± 5%, and T
A
= 25°C, unless otherwise
noted. Minimum and maximum values are given over the full VDD and T
A
(−40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE
VDD3_PLL1, Supply Voltage for PLL1
VDD3_PLL2, Supply Voltage for PLL2
VDD3_REF, Supply Voltage Clock Output Drivers Reference
VDD3_OUT[x:y],
1
Supply Voltage Clock Output Drivers
VDD1.8_OUT[x:y],
1
Supply Voltage Clock Dividers
TEMPERATURE
Ambient Temperature Range, T
A
Junction Temperature, T
J
1
Min
Typ
3.3
3.3
3.3
3.3
1.8
Max
Unit
V
V
V
V
V
Test Conditions/Comments
3.3 V ± 5%
3.3 V ± 5%
3.3 V ± 5%
3.3 V ± 5%
1.8 V ± 5%
−40
+25
+85
115
°C
°C
x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 41 and Pin 40,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 38 and Pin 37, respectively).
SUPPLY CURRENT
Table 2.
Parameter
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL1, Supply Voltage for PLL1
VDD3_PLL2, Supply Voltage for PLL2
VDD3_REF, Supply Voltage Clock Output Drivers
Reference
LVPECL Mode
LVDS Mode
HSTL Mode
CMOS Mode
VDD1.8_OUT[x:y],
1
Supply Voltage Clock Dividers
2
CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF
LVDS Mode, 7 mA
VDD3_OUT[x:y],
1
Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],
1
Supply Voltage Clock Output Drivers
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],
1
Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],
1
Supply Voltage Clock Output Drivers
LVPECL Compatible Mode
VDD3_OUT[x:y],
1
Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],
1
Supply Voltage Clock Output Drivers
HSTL Mode, 8 mA
VDD3_OUT[x:y],
1
Supply Voltage Clock Output Drivers
CMOS Mode (Single-Ended)
VDD3_OUT[x:y],
1
Supply Voltage Clock Output Drivers
Min
Typ
37
67
Max
43
77.7
Unit
mA
mA
Test Conditions/Comments
Decreases by 9 mA typical if REFB is turned
off
5
4
3
3
3.5
6
4.8
3.6
3.6
4.2
mA
mA
mA
mA
mA
Only one output driver turned on; for each
additional output that is turned on, the current
increments by 1.2 mA maximum
Only one output driver turned on; for each
additional output that is turned on, the current
increments by 1.2 mA maximum
Values are independent of the number of
outputs turned on
Values are independent of the number of
outputs turned on
Current for each divider: f = 245.76 MHz
Channel x control register, Bit 4 = 0
f = 122.88 MHz
f = 983.04 MHz
f = 122.88 MHz
f = 983.04 MHz
f = 122.88 MHz
f = 983.04 MHz
f = 122.88 MHz
f = 15.36 MHz, 10 pF load
11.5
40
6.5
23
13
41
14
2
Rev. F | Page 4 of 56
13.2
45
7.5
26.3
14.4
46.5
16.3
2.4
mA
mA
mA
mA
mA
mA
mA
mA
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