SU5726485D8ELCU
August 23, 2004
Ordering Information
Part Numbers
SM5726485D8ELCG
SB5726485D8ELCG
Description
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx8 (Stacked - two 32Mx8) Based, DDR266A, 25.40mm.
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx8 (Stacked - two 32Mx8) Based, DDR266A, 25.40mm,
Lead-Free Module.
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx8 (Stacked - two 32Mx8) Based, DDR266A, 25.40mm,
Mixed Process Module.
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx8 (Stacked - two 32Mx8) Based, DDR266A, 25.40mm,
Green Module.
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx8 (Stacked - two 32Mx8) Based, DDR266B, 25.40mm.
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx8 (Stacked - two 32Mx8) Based, DDR266B, 25.40mm,
Lead-Free Module.
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx8 (Stacked - two 32Mx8) Based, DDR266B, 25.40mm,
Mixed Process Module.
64Mx72 (512MB), DDR, 184-pin DIMM, Registered, ECC,
64Mx8 (Stacked - two 32Mx8) Based, DDR266B, 25.40mm,
Green Module.
Module Speed
PC2100 @ CL 2.0, 2.5
PC2100 @ CL 2.0, 2.5
SX5726485D8ELCG
PC2100 @ CL 2.0, 2.5
SG5726485D8ELCG
PC2100 @ CL 2.0, 2.5
SM5726485D8ELCH
SB5726485D8ELCH
PC2100 @ CL 2.5
PC2100 @ CL 2.5
SX5726485D8ELCH
PC2100 @ CL 2.5
SG5726485D8ELCH
PC2100 @ CL 2.5
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
Unit 5, Herriard Business Park, Herriard, Basingstoke, Hampshire, RG25 2PN, UK • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SU5726485D8ELCU
August 23, 2004
Revision History
• August 23, 2004
Changed the datasheet part number from SM5726485D8ELCU to SU5726485D8ELCU because of the addition
of new Module Process Technologies.
Added SB5726485D8ELCG, SX5726485D8ELCG, SG5726485D8ELCG, SB5726485D8ELCH,
SX5726485D8ELCH & SG5726485D8ELCH to the datasheet to represent the new Module Process Technolo-
gies.
• August 4, 2004
Updated the datasheet with the new Smart Modular logo.
Removed SM5726485D8ELCA from the datasheet because the new Vendor die revision does not support
DDR200.
• September 8, 2003
Modified physical dimensions in the mechanical drawing on page 7.
Updated byte 22 device attribute from 80h to C0h on page 8.
Updated SPD for byte 41 to 45 up to the DDR specification on page 9.
Added MR, EMR and Command on page 11, 12 & 13.
Changed V
DDSPD
max from 2.7 to 5.5 on page 14.
• June 26, 2001
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
Unit 5, Herriard Business Park, Herriard, Basingstoke, Hampshire, RG25 2PN, UK • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SU5726485D8ELCU
August 23, 2004
512MByte (64Mx72) DDR SDRAM Module - 64Mx8 based (Stacked - two 32Mx8)
184-pin DIMM, Registered, ECC
Features
•
•
•
•
•
•
•
Standard
:
Configuration
:
Cycle Time
:
CAS# Latency
:
Burst Length
:
Burst Type
:
No. of Internal
Banks per SDRAM :
JEDEC
ECC
7.5ns
3.0, 3.5 (Device = 2.0, 2.5)
2, 4, 8
Sequential/Interleave
4
•
•
•
•
•
•
•
Operating Voltage :
2.5V
Refresh
:
8K/64ms
Device Physicals :
400mil
Lead Finish
:
Gold
Length x Height
:
133.35mm x 25.40mm
No. of sides
:
Double-sided
Mating Connector (Examples)
Vertical
:
AMP-390241-1
184-pin DDR DIMM Pin List
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
Pin Pin
Pin Pin
Pin Pin
Pin Pin
No. Name No. Name No. Name No. Name
24
25
26
27
28
29
30
31
32
DQ17 47
DQS2 48
V
SS
A9
49
50
DQS8 70
A0
CB2
V
SS
CB3
BA1
71
72
73
74
75
V
DD
NC
DQ48
DQ49
V
SS
NC
NC
93
94
95
96
97
98
99
V
SS
DQ4
DQ5
V
DDQ
DM0/DQS9
DQ6
DQ7
Pin Pin
No. Name
116 V
SS
117 DQ21
118 A11
Pin Pin
No. Name
139 V
SS
141 A10
Pin Pin
No. Name
162 DQ47
140 DM8/DQS17 163 NC
164 V
DDQ
165 DQ52
166 DQ53
167 NC
168 V
DD
169 DM6/DQS15
170 DQ54
171 DQ55
119 DM2/DQS11 142 CB6
120 V
DD
121 DQ22
122 A8
123 DQ23
124 V
SS
125 A6
126 DQ28
127 DQ29
128 V
DDQ
143 V
DDQ
144 CB7
145 V
SS
146 DQ36
147 DQ37
148 V
DD
DQ18 51
A7
52
V
DDQ
53
DQ19 54
A5
55
DQ32 76
V
DDQ
77
DQ33 78
DQS4 79
DQ34 80
V
SS
BA0
81
82
V
DDQ
100 V
SS
DQS6 101 NC
DQ50
DQ51
V
SS
102 NC
103 NC
104 V
DDQ
RESET# 33
V
SS
DQ8
DQ9
DQS1
V
DDQ
NC
NC
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ24 56
V
SS
57
149 DM4/DQS13 172 V
DDQ
150 DQ38
151 DQ39
173 NC
174 DQ60
175 DQ61
176 V
SS
177 DM7/DQS16
178 DQ62
179 DQ63
180 V
DDQ
181 SA0
DQ25 58
DQS3 59
A4
V
DD
60
61
V
DDID
105 DQ12
DQ56
DQ57
V
DD
106 DQ13
DQ35 83
DQ40 84
V
DDQ
85
WE#
86
129 DM3/DQS12 152 V
SS
153 DQ44
154 RAS#
155 DQ45
156 V
DDQ
157 CS0#
158 CS1#
107 DM1/DQS10 130 A3
108 V
DD
131 DQ30
132 V
SS
133 DQ31
134 CB4
135 CB5
136 V
DDQ
137 CK0
138 CK0#
DQ26 62
DQ27 63
A2
V
SS
A1
CB0
CB1
V
DD
64
65
66
67
68
69
DQS7 109 DQ14
DQ58
DQ59
V
SS
NC
SDA
SCL
110 DQ15
111 CKE1
112 V
DDQ
113 NC
114 DQ20
115 A12
DQ41 87
CAS# 88
V
SS
89
DQS5 90
DQ42 91
DQ43 92
159 DM5/DQS14 182 SA1
160 V
SS
161 DQ46
183 SA2
184 V
DDSPD
( All specifications of this device are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
Unit 5, Herriard Business Park, Herriard, Basingstoke, Hampshire, RG25 2PN, UK • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SU5726485D8ELCU
August 23, 2004
Pin Description Table
Symbol
CK0
CK0#
CKE0, CKE1
CS0#, CS1#
RAS#, CAS#,
WE#
BA0, BA1
A0~A9,
A10/AP,
A11~A12
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Polarity
Positive
Edge
Negative
Edge
Active High
Active Low
Active Low
-
-
Function
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
(All DDR SDRAM addr/cntl inputs are sampled on the rising edge of their associated clocks.)
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM
PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deacti-
vating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the oper-
ations to be executed by the SDRAM.
Selects which of the four internal SDRAM banks is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when
sampled at the rising clock edge. In addition to the column address, A10/AP is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If AP is high, autopre-
charge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autopre-
charge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state
of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
Data and Check Bit Input/Output pins.
Data strobe for input and output data.
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DM0/DQS9 ~
DM8/DQS17
SA0~SA2
SDA
SCL
RESET#
V
DD,
V
SS
V
REF
V
DDQ
V
DDSPD
V
DDID
NC
SSTL
SSTL
-
Negative &
Positive
Edge
-
-
-
Active Low
-
-
-
-
-
-
LVTTL
LVTTL
LVTTL
LV-
CMOS
Supply
Supply
Supply
Supply
Supply
-
These signals are tied on the system to either V
SS
or V
DD
to configure the serial SPD.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must
be connected on the system board from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected on the system board from the SCL bus line to V
DD
to act as a pullup.
This signal is asynchronous and driven low to the register to guarantee that the register out-
puts are low.
Power and ground for the DDR SDRAM input buffers and core logic.
Reference voltage for SSTL2 inputs.
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity.
Serial EEPROM positive power supply (wired to a separate power pin at the connector which
supports both 2.3 Volt and 3.3 Volt operation).
V
DD
Indentification Flag.
No Connection.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
Unit 5, Herriard Business Park, Herriard, Basingstoke, Hampshire, RG25 2PN, UK • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SU5726485D8ELCU
August 23, 2004
Block Diagram
RCS0#
RCS1#
RCKE0
RCKE1
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22Ω
22Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U1_0
U1_1
U6_0
U6_1
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U2_0
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
U2_1
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U7_0
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U7_1
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U3_0
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U3_1
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U8_0
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U8_1
DQS5
DM5/DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
22
Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U4_0
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
DQS7
DM7/DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U4_1
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U9_0
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U9_1
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U5_0
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U5_1
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
Unit 5, Herriard Business Park, Herriard, Basingstoke, Hampshire, RG25 2PN, UK • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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