SIT5155AECFKB28IR-24.553500T datasheet, PDF

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SIT5155AECFKB28IR-24.553500T: DescriptionClipped Sine Output Oscillator, 24.5535MHz Nom, QFN-10; CategoryPassive components oscillator; File Size2MB，38 Pages; ManufacturerSiTime; Environmental Compliance

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SIT5155AECFKB28IR-24.553500T Overview

Clipped Sine Output Oscillator, 24.5535MHz Nom, QFN-10

SIT5155AECFKB28IR-24.553500T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	145208292507
package instruction	QFN-10
Reach Compliance Code	unknown
Other features	ENABLE/DISABLE FUNCTION
Ageing	1 PPM/FIRST YEAR
Frequency Adjustment - Mechanical	NO
frequency stability	0.5%
Installation features	SURFACE MOUNT
Number of terminals	10
Nominal operating frequency	24.5535 MHz
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
Oscillator type	CLIPPED SINE
Output impedance	10000 Ω
Output level	0.8 V
Package body material	CERAMIC
Encapsulate equivalent code	LCC10,.12X.2,58/52/48
physical size	5.15mm x 3.35mm x 1.06mm
Maximum slew rate	53 mA
Maximum supply voltage	3.08 V
Minimum supply voltage	2.52 V
Nominal supply voltage	2.8 V
surface mount	YES

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SiT5155

±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS

Description

The

SiT5155

is a ±0.5 ppm MEMS Super-TCXO that is

Features

◼

engineered for high reliability, GNSS-based precision

positioning and timing applications.

Leveraging SiTime’s unique DualMEMS™ temperature

sensing and TurboCompensation™ technologies, the

SiT5155 delivers the best dynamic performance for timing

stability in the presence of environmental stressors such as

air flow, temperature perturbation, vibration, shock, and

electromagnetic interference. This device also integrates

multiple on-chip regulators to filter power supply noise,

eliminating the need for a dedicated external LDO.

The SiT5155 offers three device configurations that can be

ordered using

Ordering Codes

for:

◼

12 frequencies from 10 MHz to 40 MHz

Factory programmable options for short lead time

Best dynamic stability under airflow, thermal shock

▪

±0.5 ppm stability across temperature

▪

±15 ppb/°C typical frequency slope (ΔF/ΔT)

-40°C to +105°C operating temperature

No activity dips or micro jumps

Resistant to shock, vibration and board bending

On-chip regulators eliminate the need for external LDOs

Digital frequency pulling (DCTCXO) via I

▪

Digital control of output frequency and pull range

▪

Up to

±3200

ppm pull range

▪

Frequency pull resolution down to 5 ppt

2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage

LVCMOS or clipped sinewave output

RoHS and REACH compliant

Pb-free, Halogen-free, Antimony-free

Applications

◼

The SiT5155 can be factory programmed for specific

combinations of frequency, voltage, and pull range.

Programmability enables designers to optimize clock

configurations while eliminating long lead times and

customization costs associated with quartz devices where

each frequency is custom built.

Refer to

Manufacturing Guideline

for proper reflow profile

and PCB cleaning recommendations to ensure best

performance.

◼

Precision GNSS systems

Microwave backhaul

Professional audio and video equipment

Network routers and switches

Storage and servers

Test and measurement

Block Diagram

5.0 mm x 3.2 mm Package Pinout

SDA / NC

OE / VC / NC

SCL / NC

GND

VDD

CLK

A0 / NC

Figure 1. SiT5155 Block Diagram

Figure 2. Pin Assignments (Top view)

(Refer to

Table 13

for Pin Descriptions)

Rev 1.04

May 23, 2020

www.sitime.com

SiT5155

±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS

TABLE OF CONTENTS

Description ................................................................................................................................................................................... 1

Features....................................................................................................................................................................................... 1

Applications ................................................................................................................................................................................. 1

Block Diagram ............................................................................................................................................................................. 1

5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1

Ordering Information .................................................................................................................................................................... 2

Electrical Characteristics.............................................................................................................................................................. 4

Device Configurations and Pin-outs ............................................................................................................................................. 9

Pin-out Top Views................................................................................................................................................................. 9

Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10

Waveforms................................................................................................................................................................................. 12

Timing Diagrams ........................................................................................................................................................................ 13

Typical Performance Plots ......................................................................................................................................................... 14

Architecture Overview ................................................................................................................................................................ 16

Frequency Stability ............................................................................................................................................................. 16

Output Frequency and Format ............................................................................................................................................ 16

Output Frequency Tuning ................................................................................................................................................... 16

Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 17

Device Configurations ................................................................................................................................................................ 17

TCXO Configuration ........................................................................................................................................................... 17

VCTCXO Configuration ...................................................................................................................................................... 18

DCTCXO Configuration ...................................................................................................................................................... 19

VCTCXO-Specific Design Considerations ................................................................................................................................. 20

Linearity .............................................................................................................................................................................. 20

Control Voltage Bandwidth ................................................................................................................................................. 20

FV Characteristic Slope K

................................................................................................................................................. 20

Pull Range, Absolute Pull Range ........................................................................................................................................ 21

DCTCXO-Specific Design Considerations ................................................................................................................................. 22

Pull Range and Absolute Pull Range .................................................................................................................................. 22

Output Frequency ............................................................................................................................................................... 23

C Control Registers .......................................................................................................................................................... 25

Register Descriptions.......................................................................................................................................................... 25

Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 25

Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 26

[15]

......................................................................................... 27

Serial Interface Configuration Description .......................................................................................................................... 28

Serial Signal Format ........................................................................................................................................................... 28

Parallel Signal Format ........................................................................................................................................................ 29

Parallel Data Format ........................................................................................................................................................... 29

C Timing Specification ...................................................................................................................................................... 31

C Device Address Modes ................................................................................................................................................. 32

Schematic Example ............................................................................................................................................................ 33

Dimensions and Patterns ........................................................................................................................................................... 34

Layout Guidelines ...................................................................................................................................................................... 35

Manufacturing Guidelines .......................................................................................................................................................... 35

Additional Information ................................................................................................................................................................ 36

Revision History ......................................................................................................................................................................... 37

Rev 1.04

Page 3 of 38

www.sitime.com

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