LOW Output Enable (OE) and three-state drivers. These de-
vices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Writing to the device is accomplished by taking Chip Enable
one (CE
1
) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able one (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
Functional Description
The CY62128V family is composed of three high-performance
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE
1
), an active HIGH Chip Enable (CE
2
), an active
Logic Block Diagram
Pin Configurations
Top View
SOIC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
INPUT BUFFER
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
512x 256x 8
ARRAY
62128V-2
CE
1
CE
2
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
62128V-1
A
4
A
5
A
6
A
7
A
12
A
14
A
16
NC
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TSOP I
Reverse Pinout
Top View
(not to scale)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
A
10
OE
62128V-3
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I / STSOP
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
62128V-4
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 27, 2000
CY62128V Family
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................–0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
1.6V to 3.6V
1.6V to 3.6V
Product Portfolio
Power Dissipation (Commercial)
V
CC
Range
Product
CY62128V
CY62128V25
CY62128V18
Min.
2.7V
2.3V
1.6V
Typ.
[2]
3.0V
2.5V
1.8V
Max.
3.6V
2.7V
2.0V
Speed
55, 70 ns
100 ns
200 ns
Operating (I
CC
)
Typ.
[2]
20 mA
15 mA
10 mA
Maximum
40 mA
20 mA
15 mA
Typ.
[2]
0.4
µA
0.3
µA
0.3
µA
Standby (I
SB2
)
Maximum
100
µA
(XL = 10
µA)
50
µA
(LL = 12
µA)
30
µA
(LL = 10
µA)
Electrical Characteristics
Over the Operating Range
CY62128V-55/70
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply
Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l,
70 ns
Ind’l,
55 ns
Ind’l,
70 ns
I
SB1
Automatic CE
Power-Down Current—
TTL Inputs
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Com’l,
70 ns
Coml,
55 ns
Ind’l
L
LL, XL
LL
L
LL
L
LL, XL
LL
L
LL
Test Conditions
V
CC
= Min., I
OH
= –1.0 mA
V
CC
= Min., I
OL
= 2.1 mA
Min.
2.4
0.4
2
–0.5
–1
–1
±1
±1
20
20
23
20
20
15
15
17
15
15
V
CC
+0.5V
0.8
+1
+1
40
40
50
40
40
300
300
350
300
300
µA
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC
Typ., T
A
= 25°C.
2
CY62128V Family
Electrical Characteristics
Over the Operating Range
CY62128V-55/70
Parameter
I
SB2
Description
Automatic CE
Power-Down Current—
CMOS Inputs
Test Conditions
Max. V
CC
,
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V, f = 0
Com’l
L
LL
XL
Ind’l
L
LL
Min.
Typ.
[2]
0.4
Max.
100
15
10
100
30
Unit
µA
µA
µA
µA
µA
Electrical Characteristics
Over the Operating Range
CY62128V25-100
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply
Current
Automatic CE
Power-Down Current—
TTL Inputs
Automatic CE
Power-Down Current—
CMOS Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output
Disabled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V, f = 0
Indust’l Temp Range
L
LL
L
LL
L
LL
LL
0.4
50
12
24
0.4
30
10
20
µA
µA
µA
15
300
5
100
µA
Test Conditions
V
CC
= Min., I
OH
= –0.1 mA
V
CC
= Min., I
OL
= 0.1 mA
2
–0.5
–1
–1
±1
±1
15
Min.
2.4
0.4
V
CC
+0.5
0.8
+1
+1
20
0.7*
V
CC
–0.5
–1
–1
±0.1
±0.1
10
Typ.
[2]
Max.
CY62128V18-200
Min.
0.8*
V
CC
0.2
V
CC
+0.3
0.3*
V
CC
+1
+1
15
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB1
I
SB2
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.0V
Max.
6
8
Unit
pF
pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
3
CY62128V Family
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
R2
1.8V
10%
GND
< 5 ns
62128V–5
ALL INPUT PULSES
90%
90%
10%
< 5 ns
62128V–6
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
V
OUTPUT
Parameters
R1
R2
R
TH
V
TH
3.3V
1213
1378
645
1.75V
2.5V
15909
4487
3500
0.55V
1.8V
10800
4154
3000
0.50V
Unit
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
Com’l L
LL,
XL
Ind’l
t
CDR[3]
t
R
L
LL
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= 2V
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
No input may exceed
V
CC
+0.3V
0
t
RC
Conditions
[4]
Min.
1.6
0.4
10
10
20
20
Typ.
[2]
Max.
Unit
V
µA
µA
µA
µA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
1.8V
t
CDR
CE
C62128V–7
V
DR
> 1.6 V
1.8V
t
R
Note:
4. No input may exceed V
CC
+0.3V.
4
CY62128V Family
Data Retention Current Graph
(for “L” version only)
CURRENT
DATA RETENTION
vs. SUPPLY VOLTAGE
80
SUPPLY CURRENT
(µA)
70
60
50
40
30
20
10
0
2.6
1.6
3.6
T
A
=25°C
SUPPLY VOLTAGE (V)
Switching Characteristics
Over the Operating Range
[5]
62128V-55
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
5.
6.
7.
8.
9.
62128V-70
Min.
70
Max.
62128V25-100
Min.
100
Max.
62128V18-200
Min.
200
Max.
Unit
ns
200
10
200
125
10
75
10
75
0
200
200
190
190
0
0
125
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
15
ns
ns
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
Min.
55
Max.
55
5
55
20
10
20
10
20
0
55
55
45
45
0
0
45
25
0
20
5
5
70
60
60
0
0
55
30
0
0
10
10
10
70
10
70
35
10
25
10
25
0
70
100
100
100
0
0
90
60
0
25
10
100
100
75
50
50
100
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[6, 7]
WE HIGH to Low Z
[6]
50
Test conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE signals must be LOW and CE
2
HIGH to initiate a
write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
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