Features
•
Medium-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
– 5.0(V
CC
= 4.5V to 5.5V)
– 2.7 (V
CC
= 2.7V to 5.5V)
Extended Temperature Range –40°C to 125°C
User-selectable Internal Organization
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
Three-wire Serial Interface
Sequential Read Operation
2 MHz Clock Rate (5V)
Self-timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
Description
The AT93C56A/66A provides 2048/4096 bits of serial electrically-erasable program-
mable read-only memory (EEPROM). The EEPROM is organized as 128/256 words of
16 bits each when the ORG pin is connected to VCC and 256/512 words of 8 bits each
when it is tied to ground. The device is optimized for use in many automotive applica-
tions where low-power and low-voltage operations are essential. The AT93C56A/66A
is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP
packages.
The AT93C56A/66A is enabled through the Chip Select (CS) pin and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed and no separate erase cycle is required before write. The write cycle is only
enabled when the part is in the Erase/Write Enable state. When CS is brought high
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part.
The AT93C56A/66A is available in 2.7V to 5.5V versions.
Table 1.
Pin Configuration
Pin Name
CS
SK
DI
DO
GND
VCC
ORG
DC
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Internal Organization
Don’t Connect
CS
SK
DI
DO
CS
SK
DI
DO
CS
SK
DI
DO
8-lead
PDIP
Three-wire
Serial
Extended
Temperature
EEPROMs
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
AT93C56A
AT93C66A
Preliminary
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
8-lead SOIC
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
8-lead
TSSOP
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
Rev. 5091A–SEEPR–10/04
1
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature
.........................................−65°C
to +150°C
Voltage on Any Pin
with Respect to Ground
........................................ −1.0V
to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Figure 1.
Block Diagram
16384/32768 x
8
Note:
When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground, the “x 8” organiza-
tion is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the
internal 1 Meg ohm pullup, then the “x 16” organization is selected.
2
AT93C56A/66A [Preliminary]
5091A–SEEPR–10/04
AT93C56A/66A [Preliminary]
Table 1.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted)
Symbol
C
OUT
C
IN
Note:
Test Conditions
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
1. This parameter is characterized and is not 100% tested.
Max
5
5
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
Table 2.
DC Characteristics
Applicable over recommended operating range from: T
AE
=
−40°C
to +125°C, V
CC
= +2.7V to +5.5V (unless otherwise
noted)
Symbol
V
CC1
V
CC2
I
CC
I
SB1
I
SB2
I
IL
I
OL
V
IL1(1)
V
IH1(1)
V
OL1
V
OH1
Note:
Parameter
Supply Voltage
Supply Voltage
READ at 1.0 MHz
Supply Current
Standby Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
CC
= 5.0V
V
CC
= 2.7V
V
CC
= 5.0V
V
IN
= 0V to V
CC
V
IN
= 0V to V
CC
2.7V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
I
OL
= 2.1 mA
I
OH
=
−0.4
mA
2.4
−0.6
2.0
WRITE at 1.0 MHz
CS = 0V
CS = 0V
Test Condition
Min
2.7
4.5
0.5
0.5
6.0
17
0.1
0.1
Typ
Max
5.5
5.5
2.0
2.0
10.0
30
3.0
3.0
0.8
V
CC
+ 1
0.4
V
V
Unit
V
V
mA
mA
µA
µA
µA
µA
V
1. V
IL
min and V
IH
max are reference only and are not tested.
3
5091A–SEEPR–10/04
Table 3.
AC Characteristics
Applicable over recommended operating range from T
A
=
−40°C
to + 125°C, V
CC
= As Specified, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
Symbol
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
WP
Endurance
(1)
Note:
Parameter
SK Clock Frequency
SK High Time
SK Low Time
Minimum CS
Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
CS to DO in High
Impedance
Write Cycle Time
5.0V, 25°C
Test Condition
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC Test
AC Test
AC Test
AC Test
CS = V
IL
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
0.1
1M
3
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
Min
0
0
250
250
250
250
250
250
50
50
100
100
0
100
100
250
500
250
500
250
250
100
150
10
Typ
Max
2
1
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Write Cycles
1. This parameter is characterized and is not 100% tested.
4
AT93C56A/66A [Preliminary]
5091A–SEEPR–10/04
AT93C56A/66A [Preliminary]
Functional Description
The AT93C56A/66A is accessed via a simple and versatile three-wire serial communi-
cation interface. Device operation is controlled by seven instructions issued by the host
processor.
A valid instruction starts with a rising edge of CS
and consists of a start bit
(logic “1”) followed by the appropriate op code and the desired memory address
location.
Table 4.
Instruction Set for the AT93C56A and AT93C66A
Op
Code
10
00
11
01
00
Address
x8
A
8
– A
0
11XXXXXXX
A
8
−
A
0
A
8
−
A
0
10XXXXXXX
x 16
A
7
−
A
0
11XXXXXX
A
7
−
A
0
A
7
−
A
0
10XXXXXX
D
7
−
D
0
D
15
−
D
0
x8
Data
x 16
Comments
Reads data stored in memory, at
specified address
Write enable must precede all
programming modes
Erase memory location A
n
−
A
0
Writes memory location A
n
−
A
0
Erases all memory locations. Valid
only at V
CC
= 4.5V to 5.5V
D
7
−
D
0
D
15
−
D
0
Writes all memory locations. Valid
only at V
CC
= 5.0V ±10% and Disable
Register cleared
Disables all programming instructions
Instruction
READ
EWEN
ERASE
WRITE
ERAL
SB
1
1
1
1
1
WRAL
EWDS
Note:
1
1
00
00
01XXXXXXX
00XXXXXXX
01XXXXXX
00XXXXXX
The X’s in the address field represent
don’t care
values and must be clocked.
READ (READ):
The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A
supports sequential read operations. The device will automatically increment the inter-
nal address pointer and clock out the next memory location as long as Chip Select (CS)
is held high. In this case, the dummy bit (logic “0”) will not be clocked out between mem-
ory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE ENABLE (EWEN):
To assure data integrity, the part automatically goes
into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before any programming instructions
can be carried out. Please note that once in the EWEN state, programming remains
enabled until an EWDS instruction is executed or V
CC
power is removed from the part.
ERASE (ERASE):
The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status
of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
). A
logic “1” at pin DO indicates that the selected memory location has been erased, and the
part is ready for another instruction.
5
5091A–SEEPR–10/04
京公网安备 11010802033920号
EEWORLD
