Selectable positive or negative edge synchronization
Synchronous output enable
Output frequency: 15MHz to 85MHz
3 skew grades:
IDT5V9910A-2: t
SKEW0
<250ps
IDT5V9910A-5: t
SKEW0
<500ps
IDT5V9910A-7: t
SKEW0
<750ps
3-level inputs for PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <200ps peak-to-peak
Available in SOIC package
Not Recommended for New Design
The IDT5V9910A is a high fanout phase locked-loop clock driver
intended for high performance computing and data-communications
applications. It has eight zero delay LVTTL outputs.
When the GND/sOE pin is held low, all the outputs are synchronously
enabled. However, if GND/sOE is held high, all the outputs except Q
2
and Q
3
are synchronously disabled.
Furthermore, when the V
CCQ
/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input. When V
CCQ
/
PE is held low, all the outputs are synchronized with the negative edge
of REF.
The FB signal is compared with the input REF signal at the phase
detector in order to drive the VCO. Phase differences cause the VCO of
the PLL to adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the VCO to the phase
detector. The loop filter transfer function has been chosen to provide
minimal jitter (or frequency variation) while still providing accurate
responses to input frequency changes.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
V
CCQ
/PE
GND/sOE
Q
0
Q
1
Q
2
Q
3
PLL
REF
Q
4
Q
5
FS
Q
6
Q
7
FB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2012 Integrated Device Technology, Inc.
JULY 2012
DSC 5847/3
IDT5V9910A
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
PIN CONFIGURATION
COMMERCIAL AND INDUSTRIAL TEMPERATURE
RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
I
Description
Supply Voltage to Ground
DC Input Voltage
REF Input Voltage
Maximum Power Dissipation (T
A
= 85°C)
T
STG
Storage Temperature
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–0.5 to +5.5
530
–65 to +150
Unit
V
V
V
mW
°C
REF
V
CC Q
FS
NC
V
CCQ
/PE
V
C CN
Q
0
Q
1
GND
Q
2
Q
3
V
C CN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
TES T
NC
G N D /sO E
V
C CN
Q
7
Q
6
GND
Q
5
Q
4
V
C CN
FB
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause per-
manent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute-maximum-rated condi-
tions for extended periods may affect device reliability.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
Description
Input Capacitance
Typ.
5
Max.
7
Unit
pF
SOIC
TOP VIEW
NOTE:
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not produc-
tion tested.
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
GND/
sOE
(1)
V
CCQ
/PE
FS
(2)
Type
IN
IN
IN
IN
IN
IN
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q
2
and Q
3
) in a LOW state - Q
2
and Q
3
may be used as
the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of
the reference clock.
Frequency range select:
FS = GND: 15 to 35MHz
FS = MID (or open): 25 to 60MHz
FS = V
CC
: 40 to 85MHz
Q
0
- Q
7
V
CCN
V
CCQ
GND
OUT
PWR
PWR
PWR
Eight clock output
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
NOTES:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.
2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time
before all data sheet limits are achieved.
2
IDT5V9910A
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE
RANGES
IDT5V9910A-5, -7
(Industrial)
IDT5V9910A-2
(Commercial)
Max.
3.6
+85
Min.
3
0
Max.
3.6
+70
Unit
V
°C
RECOMMENDED OPERATING RANGE
Symbol
V
CC
T
A
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
3
-40
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
(1)
Input MID Voltage
(1)
Input LOW Voltage
(1)
Input Leakage Current
(REF, FB Inputs Only)
I
3
I
PU
I
PD
V
OH
V
OL
3-Level Input DC Current (TEST, FS)
Input Pull-Up Current (V
CCQ
/PE)
Input Pull-Down Current (GND/sOE)
Output HIGH Voltage
Output LOW Voltage
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
CC
or GND
V
CC
= Max.
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
= GND
V
CC
= Max., V
IN
= GND
V
CC
= Max., V
IN
= V
CC
V
CC
= Min., I
OH
=
−
12mA
V
CC
= Min., I
OL
= 12mA
HIGH Level
MID Level
LOW Level
—
—
—
—
—
2.4
—
±200
±50
±200
±100
±100
—
0.55
μA
μA
V
V
μA
Min.
2
—
V
CC
/2
−
0.3
—
—
V
CC
−
0.6
Max.
—
0.8
—
V
CC
/2+0.3
0.6
±5
Unit
V
V
V
V
V
μA
NOTE:
1. These inputs are normally wired to V
CC
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
CC
/2. If these inputs are switched, the function and timing of the
outputs may be glitched, and the PLL may require an additional t
LOCK
time before all datasheet limits are achieved.
POWER SUPPLY CHARACTERISTICS
Symbol
I
CCQ
ΔI
CC
I
CCD
I
TOT
Parameter
Quiescent Power Supply Current
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
Total Power Supply Current
Test Conditions
(1)
V
CC
= Max., TEST = MID, REF = LOW,
GND/sOE = LOW, All outputs unloaded
V
CC
= Max., V
IN
= 3V
V
CC
= Max., C
L
= 0pF
V
CC
= 3.3V, F
REF
= 25MHz, C
L
= 160pF
(1)
V
CC
= 3.3V, F
REF
= 33MHz, C
L
= 160pF
(1)
V
CC
= 3.3V, F
REF
= 66MHz, C
L
= 160pF
(1)
NOTE:
1. For eight outputs, each loaded with 20pF.
Typ.
(2)
8
1
55
34
42
76
Max.
25
30
90
—
—
—
Unit
mA
μA
μA/MHz
mA
3
IDT5V9910A
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE
RANGES
Min.
—
3
10
15
Max.
10
—
90
85
Unit
ns/V
ns
%
MHz
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
t
PWC
D
H
R
EF
Description
(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Reference clock input
NOTE:
1. Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5V9910A-2
Symbol
F
REF
t
RPWH
t
RPWL
t
SKEW0
t
DEV
t
PD
t
ODCV
t
ORISE
t
OFALL
t
LOCK
t
JR
Parameter
FS = LOW
REF Frequency Range
REF Pulse Width HIGH
(8)
REF Pulse Width LOW
(8)
Zero Output Skew (All Outputs)
(1,3,4)
Device-to-Device Skew
(1,2,5)
REF Input to FB Propagation Delay
(1,7)
Output Duty Cycle Variation from 50%
(1)
Output Rise Time
(1)
Output Fall Time
(1)
PLL Lock Time
(1,6)
Cycle-to-Cycle Output Jitter
(1)
RMS
Peak-to-Peak
FS = MED
FS = HIGH
Min.
15
25
40
3
3
—
—
Typ.
—
—
—
—
—
0.1
—
0
0
1
1
—
—
—
Max.
35
60
85
—
—
0.25
0.75
0.25
1.2
1.2
1.2
0.5
25
200
15
25
40
3
3
—
—
IDT5V9910A-5
Min.
Typ.
—
—
—
—
—
0.25
—
0
0
1
1
—
—
—
Max.
35
60
85
—
—
0.5
1.25
0.5
1.2
1.5
1.5
0.5
25
200
15
25
40
3
3
—
—
IDT5V9910A-7
Min.
Typ.
—
—
—
—
—
0.3
—
0
0
1.5
1.5
—
—
—
Max.
35
60
85
—
—
0.75
1.65
0.7
1.2
2.5
2.5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
MHz
Unit
−
0.25
−
1.2
0.15
0.15
—
—
—
−
0.5
−
1.2
0.15
0.15
—
—
—
−
0.7
−
1.2
0.15
0.15
—
—
—
NOTES:
1. All timing and jitter tolerances apply for F
NOM
> 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. t
SKEW
is the skew between all outlets. See AC TEST LOADS.
4. For IDT5V9910A-2 t
SKEW0
is measured with C
L
= 0pF; for C
L
= 20pF, t
SKEW0
= 0.35ns Max.
5. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.)
6. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
7. t
PD
is measured with REF input rise and fall times (from 0.8V to 2V ) of 1ns.
8. Refer to INPUT TIMING REQUIREMENTS for more detail.
4
IDT5V9910A
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE
RANGES
1ns
1ns
AC TEST LOADS AND WAVEFORMS
V
CC
3.0V
2.0V
Vth =1.5V
150
Output
0.8V
0V
LVTTL Input Test Waveform
150
20p F
t
O R ISE
t
OF AL L
Test Load
2.0V
0.8V
LVTTL Output Waveform
AC TIMING DIAGRAM
t
R EF
t
R PW H
REF
t
RP W L
t
PD
t
O D CV
t
O D CV
FB
t
JR
Q
t
S K EW
t
SK E W
OTHER Q
NOTES:
Skew:
t
SKEW
:
t
DEV
:
t
ODCV
:
t
LOCK
:
The time between the earliest and the latest output transition among all outputs when all are loaded with 20pF and terminated with 75Ω to V
CC
/2.
The skew between all outputs.
The output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.)
The deviation of the output from a 50% duty cycle.
The time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until t
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