MOTOROLA
Designer's
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMDF2C02E/D
™
Data Sheet
Medium Power Surface Mount Products
Complementary TMOS
Field Effect Transistors
MMDF2C02E
COMPLEMENTARY
DUAL TMOS POWER FET
2.5 AMPERES
25 VOLTS
RDS(on) = 0.100 OHM
(N–CHANNEL)
RDS(on) = 0.25 OHM
(P–CHANNEL)
MiniMOS™ devices are an advanced series of power MOSFETs
which utilize Motorola’s TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the drain–to–source diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc–dc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
•
Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life
•
Logic Level Gate Drive — Can Be Driven by Logic ICs
•
Miniature SO–8 Surface Mount Package — Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, with Soft Recovery
•
Avalanche Energy Specified
•
Mounting Information for SO–8 Package Provided
MAXIMUM RATINGS
(TJ = 25°C unless otherwise noted)(1)
Rating
Drain–to–Source Voltage
Gate–to–Source Voltage
Drain Current — Continuous
— Pulsed
N–Channel
P–Channel
N–Channel
P–Channel
®
D
N–Channel
G
S
D
P–Channel
N–Source
N–Gate
G
S
Symbol
VDSS
VGS
ID
IDM
TJ and Tstg
PD
EAS
N–Channel
P–Channel
R
θJA
TL
245
245
62.5
260
°C/W
°C
P–Source
P–Gate
1
2
3
4
8
7
6
5
N–Drain
N–Drain
P–Drain
P–Drain
CASE 751–05, Style 14
SO–8
Top View
Value
25
±
20
3.6
2.5
18
13
– 55 to 150
2.0
Unit
Vdc
Vdc
Adc
Operating and Storage Temperature Range
Total Power Dissipation @ TA= 25°C (2)
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 20 V, VGS = 10 V, Peak IL = 9.0 A, L = 6.0 mH, RG = 25
Ω)
(VDD = 20 V, VGS = 10 V, Peak IL = 7.0 A, L = 10 mH, RG = 25
Ω)
Thermal Resistance — Junction to Ambient (2)
°C
Watts
mJ
Maximum Lead Temperature for Soldering, 0.0625″ from case. Time in Solder Bath is 10 seconds.
DEVICE MARKING
F2C02
(1) Negative signs for P–Channel device omitted for clarity.
(2) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10 sec. max.
ORDERING INFORMATION
Device
MMDF2C02ER2
Reel Size
13″
Tape Width
12 mm embossed tape
Quantity
2500 units
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 5
©
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1996
1
MMDF2C02E
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)(1)
Characteristic
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250
µAdc)
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
Gate–Body Leakage Current (VGS =
±
20 Vdc, VDS = 0)
ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250
µAdc)
Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 2.2 Adc)
(VGS = 10 Vdc, ID = 2.0 Adc)
Drain–to–Source On–Resistance
(VGS = 4.5 Vdc, ID = 1.0 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)
On–State Drain Current
(VDS = 5.0 Vdc, VGS = 4.5 Vdc)
Forward Transconductance
(VDS = 3.0 Vdc, ID = 1.5 Adc)
(VDS = 3.0 Vdc, ID = 1.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS(3)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
(VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc,
RG = 6.0
Ω)
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc,
RG = 6.0
Ω)
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 4.5 Vdc,
RG = 9.1
Ω)
(VDD = 10 Vdc, ID = 1.0 Adc,
VGS = 5.0 Vdc,
RG = 25
Ω)
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
(1) Negative signs for P–Channel device omitted for clarity.
(2) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(3) Switching characteristics are independent of operating junction temperature.
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
20
35
40
19
53
25
41
7.0
13
17
29
27
30
18
28
10.6
10
1.3
1.0
2.9
3.5
2.7
3.0
30
40
70
80
38
106
50
82
21
26
30
58
48
60
30
56
30
15
—
—
—
—
—
—
(continued)
nC
ns
(VDS = 16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
Coss
Crss
(N)
(P)
(N)
(P)
(N)
(P)
—
—
—
—
—
—
380
340
235
220
55
75
532
475
329
300
110
150
pF
V(BR)DSS
—
IDSS
IGSS
VGS(th)
—
RDS(on)
(N)
(P)
RDS(on)
(N)
(P)
ID(on)
gFS
(N)
(P)
1.0
1.0
2.6
2.8
—
—
(N)
(P)
—
—
2.0
2.0
—
—
—
—
0.200
0.400
—
—
Adc
mhos
—
—
—
—
0.100
0.250
Ohm
1.0
2.0
3.0
Ohm
(N)
(P)
—
25
—
—
—
—
—
—
—
—
1.0
1.0
100
µAdc
nAdc
Vdc
Symbol
Polarity
Min
Typ
Max
Unit
Vdc
2
Motorola TMOS Power MOSFET Transistor Device Data
MMDF2C02E
ELECTRICAL CHARACTERISTICS — continued
(TA = 25°C unless otherwise noted)(1)
Characteristic
SOURCE–DRAIN DIODE CHARACTERISTICS
(TC = 25°C)
Forward Voltage(2)
Reverse Recovery Time
see Figure 7
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc)
VSD
trr
ta
(IF = IS,
dIS/dt = 100 A/µs)
tb
QRR
(1) Negative signs for P–Channel device omitted for clarity.
(2) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
—
—
—
—
—
—
—
—
—
—
1.0
1.5
34
32
17
19
17
12
0.025
0.035
1.4
2.0
66
64
—
—
—
—
—
—
µC
Vdc
ns
Symbol
Polarity
Min
Typ
Max
Unit
TYPICAL ELECTRICAL CHARACTERISTICS
N–Channel
7
I D , DRAIN CURRENT (AMPS)
6
5
4
3.1 V
3
2.9 V
2
1
0
0
0.25
0.5
0.75
1
1.25
1.5
2.7 V
2.5 V
TJ = 25°C
1.75
2
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS = 10 V
4.5 V
4.3 V
4.1 V
4
3.7 V
3.9 V
3.3 V
I D , DRAIN CURRENT (AMPS)
3.5 V
VGS = 10 7 V
3
4.3 V
2
4.1 V
3.9 V
1
3.7 V
3.5 V
3.3 V
0
0.4
0.8
1.2
1.6
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
2
5V
4.7 V
4.5 V
TJ = 25°C
P–Channel
0
Figure 1. On–Region Characteristics
Figure 1. On–Region Characteristics
7
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
6
5
4
3
25°C
2
1
0
1.5
2
2.5
TJ = –55°C
3
3.5
4
100°C
VDS
≥
10 V
TJ = 25°C
4
VDS
≥
10 V
3
100°C
2
25°C
TJ = –55°C
1
0
2.5
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
3
3.5
4
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
4.5
Figure 2. Transfer Characteristics
Figure 2. Transfer Characteristics
Motorola TMOS Power MOSFET Transistor Device Data
3
MMDF2C02E
TYPICAL ELECTRICAL CHARACTERISTICS
N–Channel
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0.6
0.5
0.4
0.3
0.2
0.1
0
2
3
4
5
6
7
8
9
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
10
ID = 3.5 A
TJ = 25°C
0.6
0.5
0.4
0.3
0.2
0.1
0
3
4
5
6
7
8
9
10
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
ID = 1 A
TJ = 25°C
P–Channel
Figure 3. On–Resistance versus
Gate–to–Source Voltage
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0.15
TJ = 25°C
VGS = 4.5
0.1
10 V
0.6
Figure 3. On–Resistance versus
Gate–to–Source Voltage
TJ = 25°C
0.5
0.4
VGS = 4.5
0.3
0.05
0.2
10 V
0.1
0
0.5
1
ID, DRAIN CURRENT (AMPS)
1.5
2
0
0
1
2
3
4
5
6
7
ID, DRAIN CURRENT (AMPS)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
2.0
VGS = 10 V
ID = 3.5 A
1.5
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.0
VGS = 10 V
ID = 2 A
1.5
1.0
1.0
0.5
0.5
0
– 50
– 25
0
25
50
75
100
125
150
0
– 50
– 25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation
with Temperature
Figure 5. On–Resistance Variation with
Temperature
4
Motorola TMOS Power MOSFET Transistor Device Data
MMDF2C02E
TYPICAL ELECTRICAL CHARACTERISTICS
N–Channel
10000
VGS = 0 V
1000
TJ = 125°C
100°C
I DSS , LEAKAGE (nA)
TJ = 125°C
10
100
VGS = 0 V
P–Channel
I DSS , LEAKAGE (nA)
100
25°C
10
100°C
1
5
10
15
20
25
1
0
4
8
12
16
20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–to–Source Leakage Current
versus Voltage
Figure 6. Drain–to–Source Leakage Current
versus Voltage
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
Motorola TMOS Power MOSFET Transistor Device Data
5
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