Am50DL128CH
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
30776
Revision
A
Amendment
+3
Issue Date
February 6, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am50DL128CH
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Two Am29DL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation
Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM with Page Mode
DISTINCTIVE CHARACTERISTICS
MCP Features
■
Power supply voltage of 2.7 to 3.3 volt
■
High performance
— Access time as fast as 55 ns
■
20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■
Package
— 88-Ball FBGA
■
Operating Temperature
— –40°C to +85°C
■
Supports Common Flash Memory Interface (CFI)
■
Program/Erase Suspend/Erase Resume
— Suspends program/erase operations to allow
programming/erasing in same bank
Flash Memory Features
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
■
Flexible Bank™ architecture
— Read may occur in any of the three banks not being written
or erased.
— Four banks may be grouped by customer to achieve desired
bank divisions.
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
■
Manufactured on 0.13 µm process technology
■
SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
—
Customer lockable:
Sector is one-time programmable. Once
sector is locked, data cannot be changed.
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
the read mode
■
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1, 140, and
141, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
■
Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
■
Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
■
Boot sectors
— Top and bottom boot sectors in the same device
■
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
pSRAM Features
■
Power dissipation
— Operating: 50 mA maximum
— Standby: 100 µA maximum
— Deep power-down standby: 5 µA
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast as 55 ns
— Program time: 4 µs/word typical utilizing Accelerate function
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
CE1s# and CE2s Chip Select
■
Power down features using CE1s# and CE2s
■
Data retention supply voltage: 2.7 to 3.3 volt
■
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
■
8-word page mode access
■
Minimum 1 million write cycles guaranteed per sector
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
30776
Rev:
A
Amendment/+3
Issue Date:
February 6, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
Am29DL640H Features
The Am29DL640H is a 64 megabit, 3.0 volt-only flash
memory device, organized as 4,194,304 words of 16
bits each. Word mode data appears on DQ15–DQ0.
The device is designed to be programmed in-system
with the standard 3.0 volt V
CC
supply, and can also be
programmed in standard EPROM programmers.
The device is available with an access time of 55, 70
or 85 ns and is offered in a 88-ball FBGA package.
Standard control pins—chip enable (CE#f), write en-
able (WE#), and output enable (OE#)—control normal
read and write operations, and avoid bus contention
issues.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a d va n t a g e c o m p a r e d t o s ys te m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and soft-
ware integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into
four banks,
two 8 Mb banks with small and
large sectors, and two 24 Mb banks of large sectors
only. Sector addresses are fixed, system software can
be used to form user-defined bank groups.
During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can im-
prove overall system performance by allowing a host
system to program or erase in one bank, then
immediately and simultaneously read from the other
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.
The Am29DL640H can be organized as both a top and
bottom boot sector configuration.
Bank
Bank 1
Bank 2
Bank 3
Bank 4
Megabits
8 Mb
24 Mb
24 Mb
8 Mb
Sector Sizes
Eight 4 Kword,
Fifteen 32 Kword
Forty-eight 32 Kword
Forty-eight 32 Kword
Eight 4 Kword,
Fifteen 32 Kword
The
SecSi™ (Secured Silicon) Sector
is an extra
256 byte sector capable of being permanently locked
by AMD or customers. The
SecSi Indicator Bit
(DQ7)
is permanently set to a 1 if the part is
factory locked,
and set to a 0 if
customer lockable.
This way, cus-
tomer lockable parts can never be used to replace a
factory locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
2
Am50DL128CH
February 6, 2004
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram . . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations—Flash Word Mode .....................11
Erase Suspend/Erase Resume Commands ........................... 29
Table 11. Am29DL640H Command Definitions ..............................30
Flash Write Operation Status . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ................................................................. 31
Figure 6. Data# Polling Algorithm .................................................. 31
RY/BY#: Ready/Busy# ............................................................ 32
DQ6: Toggle Bit I .................................................................... 32
Figure 7. Toggle Bit Algorithm ........................................................ 32
Flash Device Bus Operations . . . . . . . . . . . . . . . 12
Word Configuration ................................................................. 12
Requirements for Reading Array Data ................................... 12
Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 12
Simultaneous Read/Write Operations with Zero Latency ....... 12
Standby Mode ........................................................................ 12
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 13
Table 2. Am29DL640H Sector Architecture ....................................14
Table 3. Bank Address ....................................................................17
Table 4. SecSi™ Sector Addresses ...............................................17
DQ2: Toggle Bit II ................................................................... 33
Reading Toggle Bits DQ6/DQ2 ............................................... 33
DQ5: Exceeded Timing Limits ................................................ 33
DQ3: Sector Erase Timer ....................................................... 33
Table 12. Write Operation Status ................................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 8. Maximum Negative Overshoot Waveform ...................... 35
Figure 9. Maximum Positive Overshoot Waveform ........................ 35
ESD Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ESD Immunity ......................................................................... 36
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37
CMOS Compatible .................................................................. 37
pSRAM DC & Operating Characteristics . . . . . . 38
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 39
Figure 10. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 39
Figure 11. Typical I
CC1
vs. Frequency ............................................ 39
Sector/Sector Block Protection and Unprotection .................. 18
Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................18
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 12. Test Setup .................................................................... 40
Figure 13. Input Waveforms and Measurement Levels ................. 40
Write Protect (WP#) ................................................................ 18
Table 6. WP#/ACC Modes ..............................................................19
Temporary Sector Unprotect .................................................. 19
Figure 1. Temporary Sector Unprotect Operation ...........................19
Figure 2. In-System Sector Protect/Unprotect Algorithms ..............20
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 41
CE#s Timing ........................................................................... 41
Figure 14. Timing Diagram for Alternating
Between Pseudo SRAM to Flash ................................................... 41
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 21
Figure 3. SecSi Sector Protect Verify ..............................................22
Read-Only Operations ........................................................... 42
Figure 15. Read Operation Timings ............................................... 42
Hardware Reset (RESET#) .................................................... 43
Figure 16. Reset Timings ............................................................... 43
Hardware Data Protection ...................................................... 22
Low V
CC
Write Inhibit ........................................................... 22
Write Pulse “Glitch” Protection ............................................ 22
Logical Inhibit ...................................................................... 22
Power-Up Write Inhibit ......................................................... 22
Common Flash Memory Interface (CFI) . . . . . . . 22
Table 7. CFI Query Identification String ..........................................23
Table 8. System Interface String .....................................................23
Table 9. Device Geometry Definition ..............................................24
Table 10. Primary Vendor-Specific Extended Query ......................25
Erase and Program Operations .............................................. 44
Figure 17. Program Operation Timings .......................................... 45
Figure 18. Accelerated Program Timing Diagram .......................... 45
Figure 19. Chip/Sector Erase Operation Timings .......................... 46
Figure 20. Back-to-back Read/Write Cycle Timings ...................... 47
Figure 21. Data# Polling Timings (During Embedded Algorithms) . 47
Figure 22. Toggle Bit Timings (During Embedded Algorithms) ...... 48
Figure 23. DQ2 vs. DQ6 ................................................................. 48
Temporary Sector Unprotect .................................................. 49
Figure 24. Temporary Sector Unprotect Timing Diagram .............. 49
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 50
Flash Command Definitions . . . . . . . . . . . . . . . . 26
Reading Array Data ................................................................ 26
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 26
Word Program Command Sequence ..................................... 27
Unlock Bypass Command Sequence .................................. 27
Figure 4. Program Operation ..........................................................28
Alternate CE#f Controlled Erase and Program Operations .... 51
Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings .......................................................................... 52
Read Cycle ............................................................................. 53
Figure 27. Pseudo SRAM Read Cycle ........................................... 53
Figure 28. Page Read Timing ........................................................ 54
Write Cycle ............................................................................. 55
Figure 29. Pseudo SRAM Write Cycle—WE# Control ................... 55
Figure 30. Pseudo SRAM Write Cycle—CE#1ps Control .............. 56
Figure 31. Pseudo SRAM Write Cycle—
UB#s and LB#s Control .................................................................. 57
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Figure 5. Erase Operation ...............................................................29
February 6, 2004
Am50DL128CH
3
Power technology
京公网安备 11010802033920号
EEWORLD
