with Sem, In t, Busy
CY7C006
CY7C016
16K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Features
• True dual-ported memory cells which allow
simultaneous reads of the same memory location
• 16K x 8 organization (CY7C006)
• 16K x 9 organization (CY7C016)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: I
CC
= 140 mA (typ.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC (7C006), 64-pin (7C006) and
80-pin (7C016) TQFP
• Pin compatible and functional equivalent to
IDT7006/IDT7016
schemes are included on the CY7C006/016 to handle situa-
tions when multiple processors access the same piece of data.
Two ports are provided, permitting independent, asynchro-
nous access for reads and writes to any location in memory.
The CY7C006/016 can be utilized as a standalone
128-/144-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16-/18-bit or wider mas-
ter/slave dual-port static RAM. An M/S pin is provided for im-
plementing 16-/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi-
processor designs, communications status buffering, and du-
al-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags, BUSY and INT, are provided on each port. BUSY signals
that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Enable (CE) pin
or SEM pin.
The CY7C006 and CY7C016 are available in 68-pin PLCC
(CY7C006), 64-pin (CY7C006) TQFP and 80-pin (CY7C016) TQFP
,
.
R/W
R
CE
R
OE
R
Functional Description
The CY7C006 and CY7C016 are high-speed CMOS 16K x 8
and 16K x 9 dual-port static RAMs. Various arbitration
Logic Block Diagram
R/W
L
CE
L
OE
L
(7C016) I/O
8L
I/O
7L
I/O
0L
[1,2]
BUSY
L
I/O
CONTROL
I/O
CONTROL
I/O
8R
(7C016)
I/O
7R
I/O
0R
BUSY
R
A
13R
[1,2]
A
13L
A
0L
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
A
0R
CE
L
OE
L
R/W
L
INTERRUPT
SEMAPHORE
ARBITRATION
CE
R
OE
R
R/W
R
SEM
L
INT
L [2]
SEM
R
INT
R[2]
M/S
C006-1
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 22, 1999
CY7C006
CY7C016
Pin Configurations
(continued)
80-Pin TQFP
Top View
I/O
1L
I/O
0L
SEM
L
R/W
L
I/O
8L
OE
L
A
13L
A
12L
A
11L
CE
L
NC
A
10L
V
CC
A
9L
A
8L
A
7L
64
NC
A
6L
NC
NC
61
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
NC
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
NC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
1
2
3
4
5
6
7
8
63
62
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
9
10
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
CY7C016
29
30
31
32
33
34
35
36
37
38
39
NC
A
13R
GND
A
9R
A
8R
A
7R
I/O
7R
R/W
R
SEM
R
CE
R
A
6R
NC
NC
NC
40
20
41
I/O
8R
OE
R
A
12R
A
11R
A
10R
Pin Definitions
Left Port
I/O
0L–7L(8L)
A
0L–13L
CE
L
OE
L
R/W
L
SEM
L
Right Port
I/O
0R–7R(8R)
A
0R–13R
CE
R
OE
R
R/W
R
SEM
R
Description
Data Bus Input/Output
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight sema-
phores. The three least significant bits of the address lines will determine
which semaphore to write or read. The I/O
0
pin is used when writing to a
semaphore. Semaphores are requested by writing a 0 into the respective
location.
Interrupt Flag. INT
L
is set when right port writes location 3FFE and is
cleared when left port reads location 3FFE. INT
R
is set when left port writes
location 3FFF and is cleared when right port reads location 3FFF.
Busy Flag
Master or Slave Select
Power
Ground
INT
L
INT
R
BUSY
L
M/S
V
CC
GND
BUSY
R
3
A
5R
C006-4
CY7C006
CY7C016
Selection Guide
7C006-15
7C016-15
15
260
70
7C006-25
7C016-25
25
220
60
7C006-35
7C016-35
35
210
50
7C006-55
7C016-55
55
200
40
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current for I
SB1
(mA)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage
[4]
......................................... –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C006-15
7C016-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
I
SB3
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS
Levels)
Standby Current
(One Port CMOS Level)
GND
≤
V
I
≤
V
CC
Outputs Disabled, GND
≤
V
O
≤
V
CC
V
CC
= Max., I
OUT
= 0 mA
Com’l
Outputs Disabled
Ind
CE
L
and CE
R
≥
V
IH
,
f = f
MAX[5]
CE
L
or CE
R
≥
V
IH
,
f = f
MAX[5]
Both Ports
CE and CE
R
≥
V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V
or V
IN
≤
0.2V, f = 0
[5]
One Port
CE
L
or CE
R
≥
V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V or
V
IN
≥
0.2V, Active
Port Outputs, f = f
MAX[5]
Com’l
Ind
Com’l
Ind
Com’l
Ind
Com’l
Ind
100
150
3
15
110
170
–10
–10
170
50
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 4.0 mA
2.2
0.8
+10
+10
260
70
–10
–10
160
160
40
40
90
90
3
3
80
80
Min.
2.4
0.4
2.2
0.8
+10
+10
220
270
60
75
130
150
15
15
120
130
mA
mA
mA
mA
Typ.
Max.
2.4
0.4
7C006-25
7C016-25
Min.
Typ. Max. Unit
V
V
V
V
µA
µA
mA
I
SB4
Notes:
4. Pulse width < 20 ns.
5. f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I
SB3
.
4
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