EEWORLDEEWORLDEEWORLD

Part Number

Search

SP2-040-N108/14-95/2

Description
Board Connector, 40 Contact(s), 2 Row(s), Male, Straight, 0.079 inch Pitch, Solder Terminal, Black Insulator, Receptacle
CategoryThe connector    The connector   
File Size349KB,2 Pages
ManufacturerE-tec Interconnect Ltd.
Environmental Compliance
Download Datasheet Parametric View All

SP2-040-N108/14-95/2 Overview

Board Connector, 40 Contact(s), 2 Row(s), Male, Straight, 0.079 inch Pitch, Solder Terminal, Black Insulator, Receptacle

SP2-040-N108/14-95/2 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerE-tec Interconnect Ltd.
Reach Compliance Codecompliant
ECCN codeEAR99
Is SamacsysN
Other featuresROHS COMPLIANT
body width0.157 inch
subject depth0.185 inch
body length1.575 inch
Body/casing typeRECEPTACLE
Connector typeBOARD CONNECTOR
Contact to complete cooperationGOLD FLASH
Contact completed and terminatedTin (Sn)
Contact point genderMALE
Contact materialBRASS
contact modeRECTANGULAR
Contact resistance20 mΩ
Contact styleSQ PIN-SKT
Dielectric withstand voltage500VAC V
Insulation resistance1000000000 Ω
Insulator colorBLACK
insulator materialNYLON
JESD-609 codee3
Manufacturer's serial numberSP
Plug contact pitch0.079 inch
Match contact row spacing0.079 inch
Installation methodSTRAIGHT
Installation typeBOARD
Number of connectorsONE
PCB row number2
Number of rows loaded2
Maximum operating temperature105 °C
Minimum operating temperature-40 °C
PCB contact patternRECTANGULAR
PCB contact row spacing2.0066 mm
Plating thicknessFLASH inch
Rated current (signal)1 A
GuidelineUL
reliabilityCOMMERCIAL
Terminal length0.083 inch
Terminal pitch2.0066 mm
Termination typeSOLDER
Total number of contacts40
Base Number Matches1
No. of Pin
Single
Row
002
003
004
005
006
007
008
009
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
Dual
Row
004
006
008
010
012
014
016
018
020
022
024
026
028
030
032
034
036
038
040
042
044
046
048
050
052
054
056
058
060
062
064
066
068
070
072
074
076
078
080
Dimension(mm)
L1
2.00
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
20.00
22.00
24.00
26.00
28.00
30.00
32.00
34.00
36.00
38.00
40.00
42.00
44.00
46.00
48.00
50.00
52.00
54.00
56.00
58.00
60.00
62.00
64.00
66.00
68.00
70.00
72.00
74.00
76.00
78.00
L2
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
20.00
22.00
24.00
26.00
28.00
30.00
32.00
34.00
36.00
38.00
40.00
42.00
44.00
46.00
48.00
50.00
52.00
54.00
56.00
58.00
60.00
62.00
64.00
66.00
68.00
70.00
72.00
74.00
76.00
78.00
80.00
[NUCLEO-L552ZE review] +AT24C32 read and write operation experiment
My DS1307 calendar module contains an AT24C32EEPROM chip, which is used to store the relevant data of the Bluetooth device in the future. Therefore, the read and write operations of AT24C32 are tested...
hujj stm32/stm8
This week's topic: Let's talk about PID and share your experience. Two pieces of exquisite PID materials are included
PID is the most classic and commonly used control method, and is also the most widely used in the engineering field. Based on the traditional PID, various PIDs have been derived, such as fuzzy PID, pr...
高进 Electronics Design Contest
Live broadcast of Microchip's GoodLock project using SAM L11 and TrustFLEX ATECC608 security devices at 10:30 am today
Future Electronics has designed a unique trusted development board, GoodLock, to help designers develop and test hardware security solutions for their embedded designs. This cost-effective general-pur...
EEWORLD社区 Embedded System
Playing with AT32F437 (3) --- USB OTG peripherals encounter strange practices
[i=s]This post was last edited by RCSN on 2021-12-20 21:04[/i]This post does not make any MCU comparison, but only analyzes the problems encountered when using AT32. However, from my personal experien...
RCSN Domestic Chip Exchange
Blockchain Raisins
...
PowerAnts Talking
Shanghai is urgently recruiting FPGA development engineers with generous benefits! ! ! !
FPGA Development Engineer [Job Responsibilities]: 1. Responsible for the logic design, implementation and maintenance of FPGA system modules 2. Responsible for logic verification and debugging on FPGA...
aoshi Recruitment

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号