NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DESIGNATOR
(1)
D
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
PACKAGE
MARKING
OPA658U
ORDERING
NUMBER
OPA658U
OPA658U/2K5
OPA658UB
OPA658UB/2K5
OPA658N/250
OPA658N/3K
OPA658P
TRANSPORT
MEDIA, QUANTITY
Rails, 100
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Rails, 50
PRODUCT
OPA658
PACKAGE-LEAD
SO-8 Surface-Mount
"
OPA658
"
SO-8 Surface-Mount
"
D
"
–40°C to +85°C
"
OPA658UB
"
OPA658
"
SOT23-5
"
DBV
"
–40°C to +85°C
"
A58
"
OPA658
"
DIP-8
"
P
"
–40°C to +85°C
"
OPA658P
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View
DIP, SO
Top View
SOT23
NC
–Input
+Input
–V
S
1
2
3
4
NC = No Connection
8
7
6
5
NC
+V
S
Output
NC
Output
1
5
+V
S
–V
S
+Input
2
3
4
–Input
2
OPA658
www.ti.com
SBOS045A
ELECTRICAL CHARACTERISTICS
At T
A
= +25°C, V
S
=
±5V,
R
L
= 100Ω, and R
FB
= 402Ω, unless otherwise noted.
OPA658P, U, N
PARAMETER
FREQUENCY RESPONSE
Closed-Loop Bandwidth
(1)
CONDITION
G = +1
(2)
G = +2
G = +5
G = +10
G = +2, 2V Step
G = +2, 2V Step
G = +2, 2V Step
G = +2, 2V Step
f = 5MHz, G = +2, V
O
= 2V
PP
f = 20MHz, G= +2, V
O
= 2V
PP
f = 10MHz, 4dBm Each Tone
G = +2, NTSC, V
O
= 1.4V
PP
, R
L
= 150Ω
G = +2, NTSC, V
O
= 1.4V
PP
, R
L
= 150Ω
G = +2
V
CM
= 0V
V
S
=
±4.7
to
±5.5V
V
CM
= 0V
V
CM
= 0V
55
MIN
TYP
900
680
370
200
1700
1500
15
11.5
6
68
56
40
0.025
0.02
135
(5)
±3
±5
64
±5.7
±10
±1.1
±30
±5.5
±8
58
±30
±80
±35
±75
MAX
MIN
OPA658UB
TYP
T
(3)
T
T
T
T
T
T
T
T
T
T
T
T
T
T
±2
±4
67
T
T
T
T
±4.5
±7
MAX
UNITS
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
ns
ns
dBc
dBc
dBm
%
degrees
MHz
mV
mV
dB
µA
µA
µA
µA
400
Slew Rate
(4)
At Minimum Specified Temperature
Settling Time: 0.01%
0.1%
1%
Spurious-Free Dynamic Range
3rd-Order Intercept Point
Differential Gain
Differential Phase
Bandwidth for 0.1dB Flatness
OFFSET VOLTAGE
Input Offset Voltage
Over Temperature Range
Power-Supply Rejection Ratio
INPUT BIAS CURRENT
Noninverting
Over Temperature Range
Inverting
Over Temperature Range
NOISE
Input Voltage Noise Density
f = 100Hz
f = 2kHz
f = 10kHz
f = 1MHz
f
B
= 100Hz to 200MHz
Input Bias Current Noise Density
Inverting: f = 1MHz
Noninverting: f = 1MHz
INPUT VOLTAGE RANGE
Common-Mode Input Range
Over Temperature Range
Common-Mode Rejection
INPUT IMPEDANCE
Noninverting
Inverting
OPEN-LOOP TRANSRESISTANCE
Open-Loop Transresistance
Over Temperature Range
OUTPUT
Voltage Output
Over Temperature Range
Voltage Output
Over Temperature Range
Voltage Output
Over Temperature Range
Output Current, Sourcing
Over Temperature
Output Current, Sinking
Over Temperature
Short Circuit Current
Output Resistance
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
Over Temperature Range
TEMPERATURE RANGE
Specification: P, U, N, UB
Thermal Resistance,
θ
JA
P
DIP-8
U
SO-8
N
SOT23-5
1000
900
±18
±35
T
T
16
4.9
3.2
3.2
45.3
32
11.9
T
T
T
T
T
T
T
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVrms
pA/√Hz
pA/√Hz
V
CM
=
±1V
±2.5
45
±2.9
50
500 || 1
50
T
T
T
T
T
T
V
dB
kΩ || pF
Ω
kΩ
kΩ
V
V
V
V
V
V
mA
mA
mA
mA
mA
Ω
V
V
mA
mA
°C
°C/W
°C/W
°C/W
V
O
=
±2V,
R
L
= 100Ω
V
O
=
±2V,
R
L
= 100Ω
No Load
R
L
= 250Ω
R
L
= 100Ω
150
100
±2.7
±2.5
±2.7
±2.5
±2.2
±2.0
80
70
60
35
190
200
150
T
T
T
T
T
T
T
T
T
T
250
±2.9
±2.75
±2.9
±2.7
±2.8
±2.5
120
80
150
0.02
±5
±5
±5.5
T
T
T
T
T
T
T
T
T
T
T
0.1MHz, G = +2
V
S
=
±5V
±4.5
±5.5
±7.75
±8.5
+85
T
±4.5
±4.7
T
T
T
T
T
±5.75
±6.5
T
–40
100
125
150
(1) Frequency response can be strongly influenced by PC board parasitics. The demonstration boards show low parasitic layouts for this part. Refer to the
demonstration board layout for details.
(2) At G = +1, R
FB
= 560Ω for DIP and 402Ω for SO-8.
(3) An asterisk (T) specifies the same value as the grade to the left.
(4) Slew rate is rate of change from 10% to 90% of output voltage step.
(5) This specification is PC board layout dependent.
As the latest product of TI's C2000 series, 28377S(D), the ADC module is its core signal acquisition function. The ADC of 28377 is a successive approximation register (SAR) ADC with a selectable resol...
[i=s] This post was last edited by Lazy Cat Love Flying on 2021-8-8 00:27[/i]To be honest, I have never touched Silicon MCU before, so I have to do a lot of preparation work in the early stage. Well, ...
I just saw this news. Time really flies by so fast. There are only 40 days left for the college entrance examination. I can only wish you all the best. Come on, young people
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
