PRELIMINARY
CY22701
1 PLL In-System Programmable Clock Generator
Features
• In-system programmable through I
2
C Serial
Programming Interface (SPI)
• Programmable SRAM and non-volatile EEPROM
memory bits with 3.3V supply
• Integrated, phase-locked loop with programmable P
and Q counters, output dividers
• Low-jitter, high-accuracy outputs
• 3.3V Operation
• 8-lead SOIC
Benefits
• Custom timing solutions for designs not suitable for
factory custom silicon, Xtals, or ASICs for production
• Program and optimize designs while chip is on system
board
• Programming voltages contained in chip
• High-performance PLL enables control of output
frequencies that are customizable to support a wide
range of applications
• Meets critical timing requirements in complex system
designs
• Meets industry-standard voltage platforms
• Industry standard packaging saves on board space
Part Number
CY22701
No. of Outputs
2
Input Frequency Range
Output Frequency Range
1 – 167 MHz (Driven Clock Input) {Commercial} 80 kHz – 200 MHz (3.3V) {Commercial}
1 –150 MHz (Driven Clock Input) {Industrial}
80 kHz –167 MHz (3.3V) {Industrial}
8 – 30 MHz (Crystal Reference) {Comm. or Ind.}
Logic Block Diagram
XIN
XOUT
OUTPUT
DIVIDERS
Output
Crosspoint
Switch
Array
OSC
Q
Φ
VCO
P
PLL
CLK1
CLK2
Clock
Configuration
EEPROM
Memory Array
Pin Configuration
WP
[I
2
C- SPI:]
SCL
SDAT
XIN
VDD
VDD VSS
1
2
3
4
8
XOUT
CY22701
7
CLK2/WP
6
CLK1
5
SCL
8 PIN SOIC
SDA
VSS
Cypress Semiconductor Corporation
Document #: 38-07698 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised February 8, 2005
PRELIMINARY
Pin Description
Name
XIN
VDD
SDAT
VSS
SCL
CLK1
CLK2/WP
XOUT
[1]
Pin Number
1
2
3
4
5
6
7
8
Description
Reference crystal input
3.3V voltage supply
Data input for serial programming
Ground
Clock signal input for serial programming
Clock output 1 (Default to reference frequency)
Clock output 2/Write Protect (Default Write Protect)
Reference crystal output
CY22701
Functional Description
The CY22701 uses an EEPROM array along with on-chip
programming voltages to program the device for development,
or in production on the circuit board. An industry standard I
2
C
serial programming interface (SPI) is used to program the
scratchpad and clock core.
Clock Features
The programmable clock core is configured with the following
features:
•
Crystal Oscillator:
Programmable drive and load, support
for external references up to 167 MHz. See Reference
Frequency (REF) on page 4
•
PLL:
Programmable P, Q, offset, and loop filter parameters.
•
Outputs:
2 outputs and two programmable linear dividers.
The output swing of CLK1 and 2 is set by VDD (3.3V).
Clock configuration is stored in a dedicated 2-kbit block of
nonvolatile EEPROM and a 2-kbit block of volatile SRAM. The
SPI is used to write new configuration data to the on-chip
programmable registers that are defined within the clock
configuration memory blocks.
Serial Programming Interface (SPI)
The SPI uses industry-standard signaling in both standard and
fast modes to program the 2-kbit EEPROM dedicated to clock
configuration, and the 2-kbit SRAM block. See sections
beginning with Using the Serial Programming Interface on
page 2 for more information.
• Pin 7 is configured as Write Protect (see “Write Protect (WP)
Registers” section on page 5 to configure as CLK2)
This default clock configuration is typically customized to meet
the needs of a specific application. It provides a clock signal
upon power-on, to facilitate in-system programming. Alterna-
tively, the CY22701 may be programmed with a different clock
configuration prior to placement of the CY22701 in systems.
While you can develop your own subroutine to program any or
all of the individual registers described in the following pages,
it may be easier to use CyberClocks™ to produce the required
register setting file.
Using the Serial Programming Interface
The CY22701 provides an industry-standard serial
programming interface for volatile and nonvolatile, in-system
programming of unique frequencies and options. Serial
programming and reprogramming allows for quick design
changes and product enhancements, eliminates inventory of
old design parts, and simplifies manufacturing.
The CY22701 is a group of two slave devices with addresses
as shown in
Figure 1.
The serial programming interface
address of the CY22701 clock configuration 2-kbit EEPROM
block is 68H. The serial programming interface address of the
CY22701 clock configuration 2-kbit SRAM block is 69H.
Should there be a conflict with any other devices in your
system, both device addresses can also be changed using
CyberClocks. Registers in the clock configuration 2-kbit SRAM
memory block are written, when the user wants to update the
clock configuration for on-the-fly changes
.
Registers in the
clock configuration EEPROM block are written, if the user
wants to update the clock configuration so that it is saved and
used again after power-up or reset.
All programmable registers in the CY22701 are addressed
with eight bits and contain eight bits of data.
Table 1
lists the
specific register definitions and their allowable values. See
section Serial Programming Interface Timing on page 10, for
a detailed description.
Default Start-up Condition for CY22701
The default clock configuration is:
• The crystal oscillator circuit is active.
• CLK1 outputs REF frequency.
clock config.
EE block
256 x 8 bits
Address:
1101000
clock config.
SRAM
256 x 8 bits
Address:
1101001
Figure 1. Device Addresses for EEPROM and SRAM Clock Configuration Blocks
Note:
1. Float XOUT if XIN is externally driven.
Document #: 38-07698 Rev. *B
Page 2 of 15
PRELIMINARY
Table 1. Summary Table – CY22701 Programmable Registers
Register
09H
OCH
11H
12H
13H
40H
41H
42H
45H
47H
Description
CLKOE control
DIV1SRC mux and
DIV1N divider
Write Protect
registers
Input crystal oscillator
drive control
Input load capacitor
control
Charge Pump and PB
counter
PO counter, Q
counter
Crosspoint switch
matrix control
DIV2SRC mux and
DIV2N divider
D7
0
D6
0
D5
0
D4
CLK2
D3
CLK1
D2
0
CY22701
D1
0
D0
0
DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)
0
0
CapLoad
(7)
1
PB(7)
PO
1
0
0
CapLoad
(6)
1
PB(6)
Q(6)
0
XCapSrc
default=1
CapLoad
(5)
0
PB(5)
Q(5)
0
XDRV(1)
CapLoad
(4)
Pump(2)
PB(4)
Q(4)
WPSrc
Default=0
XDRV(0)
CapLoad
(3)
Pump(1)
PB(3)
Q(3)
1
0
CapLoad
(2)
Pump(0)
PB(2)
Q(2)
0
0
CapLoad
(1)
PB(9)
PB(1)
Q(1)
0
0
CapLoad
(0)
PB(8)
PB(0)
Q(0)
1
CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0
for CLK1 for CLK1 for CLK1 for CLK2 for CLK2 for CLK2
DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)
CLK = ((REF * Ptotal)/Qtotal)/Post Divider
CLK = REF/Post Divider
CLK = REF
The basic PLL block diagram is shown in
Figure 2.
Each of the
two clock outputs on the CY22701 has a total of seven output
options available to it. There are six post divider options
available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N
and DIV2N are independently calculated and are applied to
individual output groups. The post divider options can be
applied to the calculated VCO frequency ((REF*P)/Q) or to the
reference frequency directly.
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the reference frequency
directly to the crosspoint switch matrix.
CLKSRC
Crosspoint
Switch Matrix
/DIV1N
[45H]
CY22701 Frequency Calculation and Register
Definitions
The CY22701 is an extremely flexible clock generator with
three basic variables that can be used to determine the final
output frequency:
1. Input reference frequency (REF)
2. the internally calculated P and Q dividers
3. Post divider, which can be a fixed or calculated value.
There are three basic formulas for determining the final output
frequency of a CY22701-based design. Any one of these three
formulas may be used:
DIV1N [OCH]
DIV1SRC [OCH]
1
Q
total
CLK1
DIV1CLK
REF
(
Q+2)
[42H]
PFD
VCO
P
total
0
/2
(2(PB+4)+PO)
[40H], [41H], [42H]
1
/
3
Divider Bank 1
Divider Bank 2
/
4
/
2
/DIV2N
[45H]
DIV2CLK
0
CLK2
DIV2SRC [47H]
DIV2N [47H]
Figure 2. Basic Block Diagram of CY22701 PLL
Document #: 38-07698 Rev. *B
Page 3 of 15
PRELIMINARY
Reference Frequency (REF)
The reference frequency can be a crystal or a driven
frequency. For crystals, the frequency range must be between
8 MHz and 30 MHz. For a driven frequency, the frequency
range must be between 1 MHz and 167 MHz (Commercial
Temp.) or 150 MHz (Industrial Temp.).
Using a Crystal as the Reference Input
The input crystal oscillator of the CY22701 is an important
feature because of the flexibility it allows the user in selecting
a crystal as a reference frequency source. The input oscillator
has programmable gain, allowing for maximum compatibility
with a reference crystal, regardless of manufacturer, process,
performance and quality.
Programmable Crystal Input Oscillator Gain Settings
The Input crystal oscillator gain (XDRV) is controlled by two
bits in register 12H, and are set according to
Table 2.
The
parameters controlling the gain are the crystal frequency, the
internal crystal parasitic resistance (ESR, available from the
manufacturer), and the CapLoad setting during crystal
start-up.
Bits 3 and 4 of register 12H control the input crystal oscillator
gain setting. Bit 4 is the MSB of the setting, and bit 3 is the
LSB. The setting is programmed according to
Table 2.
All other bits in the register are reserved and should be
programmed LOW. See
Table 3
for bit locations and values.
Using an External Clock as the Reference Input
The CY22701 can also accept an external clock as reference,
with speeds up to 167 MHz (or 150 MHz at Industrial Temp.).
With an external clock, the XDRV (register 12H) bits must be
set according to
Table 4.
Table 2. Programmable Crystal Input Oscillator Gain Settings
Calculated CapLoad Value
Crystal ESR
Crystal Input
Frequency
8 – 15 MHz
15 – 20 MHz
20 – 25 MHz
25 – 30 MHz
00
01
01
10
00H – 20H
30Ω
60Ω
01
10
10
10
01
01
10
10
20H – 30H
30Ω
60Ω
10
10
10
11
01
10
10
11
Input Load Capacitors
CY22701
Input load capacitors allow the user to set the load capacitance
of the CY22701 to match the input load capacitance from a
crystal. The value of the input load capacitors is determined by
8 bits in a programmable register [13H]. The proper CapLoad
register setting is determined by the formula:
CapLoad = (C
L
– C
BRD
– C
CHIP
)/0.09375 pF
where:
• C
L
= specified load capacitance of your crystal.
• C
BRD
= the total board capacitance, due to external capac-
itors and board trace capacitance. In CyberClocks, this
value defaults to 2 pF.
• C
CHIP
= 6 pF.
• 0.09375 pF = the step resolution available due to the 8-bit
register.
In CyberClocks, only the crystal capacitance (C
L
) is specified.
C
CHIP
is set to 6 pF, and C
BRD
defaults to 2 pF. If your board
capacitance is higher or lower than 2 pF, the formula above
can be used to calculate a new CapLoad value and
programmed into register 13H.
In CyberClocks, enter the crystal capacitance (C
L
). The value
of CapLoad will be determined automatically and programmed
into the CY22701. Through the SDAT and SCLK pins, the
value can be adjusted up or down if your board capacitance is
greater or less than 2 pF. For an external clock source,
CapLoad defaults to 1. See
Table 5
for CapLoad bit locations
and values.
The input load capacitors are placed on the CY22701 die to
reduce external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency
shift that occurs when non-linear load capacitance is affected
by load, bias, supply and temperature changes.
30H – 40H
30Ω
60Ω
10
10
11
N/A
Table 3. Register Map for Input Crystal Oscillator Gain Setting
Address
12H
.
D7
0
D6
0
D5
XCapSrc, default=1
D4
D3
D2
0
D1
0
D0
0
XDRV(1) XDRV(0)
Table 4. Programmable External Reference Input Oscillator Drive Settings
Reference Frequency
Drive Setting
1–25 MHz
00
25–50 MHz
01
50–90 MHz
10
90–167 MHz
11
Table 5. Input Load Capacitor Register Bit Setting
Address
13H
D7
D6
D5
D4
D3
D2
D1
D0
CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0)
Document #: 38-07698 Rev. *B
Page 4 of 15
PRELIMINARY
DCXO
The default clock configuration of the CY22701 has 256 stored
values that are used to adjust the frequency of the crystal oscil-
lator, by changing the load capacitance. In order to use these
stored values, the clock configuration must be reprogrammed
to enable the DCXO feature.
To Configure for DCXO Operation
• XCapSrc, Register 12H[5] = 0
• XDRV[1:0], Register 12H[4:3] = (see
Table 2)
Once the clock configuration block is programmed for DCXO
operation, the SPI may be used to dynamically change the
capacitor load value on the crystal. A change in crystal load
capacitance corresponds with a change in the reference
frequency. Thus, the crystal oscillator frequency can be
adjusted from –150 ppm of the nominal frequency value to
+150 ppm of the nominal frequency value. “Nominal frequency
– 150 ppm” is achieved by writing 00000000 into the CapLoad
register, and “nominal frequency + 150 ppm” is achieved by
writing 11111111 into the CapLoad register
CY22701
PLL Frequency, Q Counter
The first counter is known as the Q counter. The Q counter
divides REF by its calculated value. Q is a 7-bit variable with
a maximum value of 127 and minimum value of 0. The primary
value of Q is determined by 7 bits in register 42H (6..0), but 2
is added to this register value to achieve the total Q, or Q
total
.
Q
total
is defined by the formula:
Q
total
= Q + 2.
The minimum value of Q
total
is 2. The maximum value of Q
total
is 129. Register 42H is defined in
Table 6.
Stable operation of the CY22701 cannot be guaranteed if
REF/Q
total
falls below 250 kHz. Q
total
bit locations and values
are defined in
Table 6.
PLL Frequency, P Counter
The next counter definition is the P (product) counter. The P
counter is multiplied with the (REF/Q
total
) value to achieve the
VCO frequency. The product counter, defined as P
total
, is
made up of two internal variables, PB and PO. The formula for
calculating P
total
is:
P
total
= (2(PB + 4) + PO)
PB is a 10-bit variable, defined by registers 40H(1:0) and
41H(7:0). The 2 LSBs of register 40H are the two MSBs of
variable PB. Bits 4..2 of register 40H are used to determine the
charge pump settings (see section, Charge Pump Settings
[40H(2..0)] on page 6”). The 3 MSBs of register 40H are preset
and reserved and cannot be changed.
PO is a single bit variable, defined in register 42H(7). This
allows for odd numbers in P
total
.
The remaining 7 bits of 42H are used to define the Q counter,
as shown in
Table 6.
The minimum value of P
total
is 8. The maximum value of P
total
is 2055. To achieve the minimum value of P
total
, PB and PO
should both be programmed to 0. To achieve the maximum
value of P
total
, PB should be programmed to 1023, and PO
should be programmed to 1.
Stable operation of the CY22701 cannot be guaranteed if the
value of (P
total
*(REF/Q
total
)) is above 400 MHz or below
100 MHz. Registers 40H, 41H and 42H are defined in
Table 7.
Write Protect (WP) Registers
To reconfigure pin 7 as WP, to control enable/disable of write
protection, use the SPI to write the following:
WPSrc, Register 11H[3] = 0
CLK2, Register 09H[4] = 0
CLKSRC 2,1,0, Register 45H[3:1] = 111
When active (WP = 1), WP prevents the control logic for the
EE from initiating a erase/program cycle for the EEPROM
blocks. All serial shifting works as normal.
To reconfigure pin 7 as CLK2, use the SPI to write the
following:
WPSrc, Register 11H[3] = 1
CLK2, Register 09H[4] = 1
CLKSRC 2,1,0, Registers 45H[3:1] = see
Table 11
Table 6. Q Counter Register Definition
Register
42H
D7
PO
D6
Q(6)
D5
Q(5)
D4
Q(4)
D3
Q(3)
D2
Q(2)
D1
Q(1)
D0
Q(0)
Table 7. P Counter Register Definition
Address
40H
41H
42H
D7
1
PB(7)
PO
D6
1
PB(6)
Q(6)
D5
0
PB(5)
Q(5)
D4
Pump(2)
PB(4)
Q(4)
D3
Pump(1)
PB(3)
Q(3)
D2
Pump(0)
PB(2)
Q(2)
D1
PB(9)
PB(1)
Q(1)
D0
PB(8)
PB(0)
Q(0)
Document #: 38-07698 Rev. *B
Page 5 of 15
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