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74LVC3G04DC

Description
IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8, Gate
Categorylogic    logic   
File Size275KB,21 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric View All

74LVC3G04DC Overview

IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8, Gate

74LVC3G04DC Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeTSSOP
package instruction2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8
Contacts8
Reach Compliance Codecompliant
Is SamacsysN
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-G8
JESD-609 codee4
length2.3 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeINVERTER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of functions3
Number of entries1
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeVSSOP
Encapsulate equivalent codeTSSOP8,.12,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup5.5 ns
propagation delay (tpd)9.5 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.65 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width2 mm
Base Number Matches1
74LVC3G04
Triple inverter
Rev. 11 — 2 April 2013
Product data sheet
1. General description
The 74LVC3G04 provides three inverting buffers.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
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