W28C64
Radiation Hardened 8K x 8 CMOS EEPROM
Northrop Grumman Corporation
May 1997
Features
•
1.25 Micrometer Radiation Hardened CMOS on Epi
−
Total Dose up to 300 Krad (Si)
−
Transient Logic Upset >5E7 Rad(Si)/sec
−
Memory Data Loss >1E12 Rad(Si)/sec
•
Single Event Upsets
−
SEU During READ
LETth = 60 MeV/mg/cm
2
−
SEU in Address/Data Latches,
LETth = 35 MeV/mg/cm
2
−
Permanent SEU damage (During Write Only),
Atomic Number
≥
Kr
•
No Latchup
•
Compatible with commercial EEPROMs
•
JEDEC pin compatible in center 32p LCC
•
Full military operating temperature range, screened to
specific test methods for commercial, Class B, or modified
Hi Rel.
•
Supports these commercial features:
−
Self-Timed Programming
−
Combined Erase/Write
−
Auto Program Start
−
+5V only read operation
−
Asynchronous Addressing
−
64 Word Page
−
Data Polling
PINOUTS
(Top Views)
C
V W P
A
A 1 N V D E E
7 2 C W D B B
A6
A5
A4
A3
A2
A1
A0
CLK
D0
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
D D V R D D D
1 2 S S 3 4 5
S T
B
VW
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
CLK
D0
D1
D2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
WEB
CPEB
A8
A9
A11
PE
OEB
A10
CEB
D7
D6
D5
D4
D3
RSTB
4 3 2 1 32 31 30 29
28
27
26
32 LCC
25
24
23
22
21
A8
A9
A11
PE
OEB
A10
CEB
D7
D6
32 FP
Introduction
The W28C64 is a 8K x 8 radiation hardened EEPROM
designed by Sandia National Laboratories, Albuquerque
NM, and manufactured by Northrop Grumman Advanced
Technology Center, Baltimore MD, using nonvolatile
memory technology transferred from Sandia. It is built using
a mature dual well CMOS process using N on N+ epitaxial
silicon and a two layer interconnect system.
Caution: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. handling procedures.
1
DC Operating Characteristics
TA = -55° to + 125°C, VDD = 5V
±5%,
unless otherwise specified
LIMITS
SYMBOL
IDDS
IDDR
IDDW
IW1
IDDSB
IIH
IIL
IOH
IOL
VIL
VIH
VOH
VOL
IOZL
IOZH
PARAMETER
Static I Read
Active I Read
Active I Write
Inactive I Write
Standby I
Input I High
Input I Low
Output I High
Output I Low
Input V Low
Input V High
Output V High
Output V Low
Tristate Leakage
Low
Tristate Leakage
High
-10
10
-3
-0.5
3.8
4.25
0.5
0.95
VDD +0.5
-25
1.5
1
1
3
MIN
MAX
10
17
2
UNITS
mA
mA
mA
uA
mA
uA
uA
mA
mA
V
V
V
V
uA
uA
VDD = 4.75 VW = -4.75 VIH = 3.8 VIL = 0.95 IOL =
-3 mA (Note 2)
VDD = 4.75 VW = -4.75 VIH = 3.8 VIL = 0.95 IOH =
3 mA (Note 2)
VOH = 4.25V
VOL = 0.5 V
TEST CONDITIONS
Read Mode, DC
Read Mode, 2 MHz
Write Mode
Standby or Read (Note 1)
Notes:
1.
Tested but not recorded
2.
Verified by functional testing
may be deselected. When the part is deselected, the
outputs are tristated.
A(12:0)
ADDR
XXX
ADDR
XXX
XXX
I/O
DOUT
HI Z
DIN
HI
Z/DOUT
HI
Z/DOUT
Mode Selection
MODE
Read
Standby
Write
Write
Inhibit
CEB
VIL
VIH
VIL
X
X
OEB
VIL
X
VIH
X
VIL
WEB
VIH
X
VIL
VIH
X
PE
VIL
VIL
VIL
VIL
VIL
Output Enable (OEB)
This input controls the output buffers. When HIGH the
outputs are tristated and when LOW the outputs are
driven to the correct CMOS levels.
Data (D0-D7)
Data is written to or read from the part using these pins.
Write Enable (WEB)
This input controls the writing of data. When low, write is
enabled.
Pin Description Addresses (A0-A12)
The address inputs select which byte will be accessed
during a read or write operation. A0-A5 are the column or
byte addresses and A6-A12 are the row or page
addresses.
Clock Input (CLK)
The clock input is used to time the programming
functions. The nominal value for a 10 ms write cycle is 2
MHz. The clock is not required for read operations. The
clock waveform has no critical timing with respect to other
input or output signals.
Chip Enable (CEB)
This input must be LOW during read and write operations.
After a programming operation has been initiated, the chip
3
Reset Input (RSTB)
The reset input is active LOW and is used to prevent
programming during power transitions or during high
transient radiation doses. This signal should be held low
during power up and power down.
silicon gate N-channel MOS transistor with a specially
processed gate dielectric consisting of a tunnelling oxide,
a silicon nitride layer, and a capping oxide. SONOS
technology is used in preference to conventional floating
gate technology because of its superior reliability and
radiation hardness.
The SONOS memory effect relies on charge storage within
the silicon nitride film, with the silicon dioxide above and
below it acting as energy barriers to the loss of charge.
The charge is injected by tunnelling through the
tunnelling oxide.
The charge deposited in the SONOS dielectric does decay
slowly with time, but when written under the specified
conditions and stored within the specified limits, data is
indeed permanent for most purposes. Data loss is
accelerated by both temperature and radiation, and is also
affected by the number of write cycles the device has seen
previously.
Write cycles must, however, be accumulated in the tens of
thousands before any effect on retention is seen. When
written using a 2 MHz external clock, nonvolatile data
storage guaranteed through 100 K Rad (Si), without
rewriting, at the specified temperature range. In satellite
applications, this normally corresponds to many years of
service.
For operation beyond 100 K Rad (Si), data should be
written after every 100 K Rad of accumulated total dose. In
addition to the memory devices themselves, a key feature
of this device is the radiation hardened peripheral
circuitry. This circuitry remains virtually unaffected by
radiation effects within the limits specified over the full
range of device operation.
For proper retention and reliability, the memory devices
require careful control of the clear/write conditions. This
applies particularly to the control of the clear/write
voltage. The clear/write time (pulsewidth) is also
important.
Consequently, both a Clock pin and a Vwrite pin are
provided. With a nominal 2 MHz clock and Vw = -5V±5%,
this device emulates commercial EEPROMs. Under these
conditions, data retention is guaranteed for a minimum of
10 years. The external clock is required for write mode
only, read mode is asynchronous and no clock is required.
Temperatur
e
Retention
(Years)
Cycles
Total Dose
K Rad (Si)
Write Voltage (VW)
This -5V±5% supply pin is used to provide the internal
programming voltage. This pin may be tied to OV during
read operations. During power up VDD must come up first,
then Vw; and during power down Vw must go off first,
then VDD.
Charge Pump Enable (CPEB)
Must be tied to VDD. Reserved for future use.
Program Enable Input (PE)
This pin is used for testing and validation purposes to
gain more control over internal chip operation. Normal
operation requires this pin to be tied LOW. In READ
ONLY (ROM) applications, this pin can be used to gain
external control of the write timing to optimize retention.
This feature is used when the device is programmed off-
line using a PROM programmer. The W28C64 is supported
by the PROM programmer supplied by BP Microsystems,
Houston, TX.
CAUTION: Device can be damaged if improperly
programmed in external mode. For ROM applications, a
PROM programmer is recommended. Contact Northrop
Grumman for additional information. The optimized
programming conditions used in the PROM programmer
will result in longer retention, when frequent
reprogramming is not a requirement. Under these
conditions retention is specified as 100 years, at 80°C, with
less than 200 programming cycles and less than 50 K Rads
total dose.
Data Polling
The programming time for the W28C64 is controlled by an
internal counter and the externally supplied clock input.
The nominal timing is for a 10 ms programming time with a
2 MHz clock input. The Data Polling mode can be used to
verify the completion of programming. If a read is
performed on any address while the part is still being pro-
grammed, the ones complement of the last byte written will
be presented at the outputs. After programming has
completed, a read of the last address written will result in
the correct data being presented at the outputs. To
monitor for completion of programming the user can read
the last address written until the correct data is read.
-55 to 80°C
-55 to 80°C
10
10*
10,000
1,000
0 to 50
50 to 100
Data Retention
The W28C64 EEPROM is based on SONOS nonvolatile
memory technology. SONOS is an acronym for Silicon-
Oxide-Nitride-Oxide-Silicon. The memory device is a
Rewriting after 100 K Rads results in another 10 years of
retention up to a max total dose specified
4
Analogue and Mixed Signal
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