3.3 V 1:6 LVCMOS PLL Clock Generator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
The MPC9331 is a 3.3 V compatible, 1:6 PLL based clock generator targeted
for high performance low-skew clock distribution in mid-range to high-performance
telecom, networking, and computing applications. With output frequencies up to
240 MHz and output skews less than 150 ps, the device meets the needs of most
the demanding clock applications. The MPC9331 is specified for the temperature
range of 0°C to +70°C.
Features
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1:6 PLL Based Low-Voltage Clock Generator
3.3 V Power Supply
Generates Clock Signals up to 240 MHz
Maximum Output Skew of 150 ps
Differential LVPECL Reference Clock Input
Alternative LVCMOS PLL Reference Clock Input
Internal and External PLL Feedback
Supports Zero-Delay Operation in External Feedback Mode
PLL Multiplies the Reference Clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3
or x/4
Synchronous Output Clock Stop in Logic Low Eliminates Output Runt Pulses
Power_Down Feature Reduces Output Clock Frequency
Drives Up to 12 Clock Lines
32-Lead LQFP Packaging
32-Lead Pb-Free Package Available
Ambient Temperature Range 0°C to +70°C
Internal Power-Up Reset
Pin and Function Compatible to the MPC931
MPC9331
DATASHEET
MPC9331
LOW VOLTAGE
3.3 V LVCMOS 1:6
CLOCK GENERATOR
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback
input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback
path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback
configuration and with the available post-PLL dividers (divide-by-2, divide-by-4, and divide-by-6), the internal VCO of the
MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration
(divide-by-8) the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a
division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC
pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4.
The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The PLL_EN
control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is
routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency
specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the
OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to
missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling
the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop
synchronously in logic low state, without the potential generation of runt pulses.
The MPC9331 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept
LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the
devices an effective fanout of 1:12. The device is packaged in a 7x7 mm
2
32-lead LQFP package.
MPC9331 REVISION 7 March 11, 2016
1
©2016 Integrated Device Technology, Inc.
MPC9331 Data Sheet
3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR
V
CC
3 x 25 K
PCLK
PCLK
CCLK
REF_SEL
Bank A
0
1
Ref
PLL
25k
1
25k
V
CC
FB_SEL
25k
V
CC
25k
PWR_DN
V
CC
25k
PLL_EN
FSELA
FSELB
FSELC
3 x 25 K
CLK_STOP0
CLK_STOP1
OE/MR
V
CC
3 x 25 K
Power_On Reset
3
0
1
CLK
Stop
QC1
0
FB
200 – 480 MHz
VCO
1
2
0
1
0
1
2
4
6
Bank B
QB0
0
1
8
CLK
Stop
QB1
Bank C
QC0
QA0
0
1
CLK
Stop
QA1
FB_IN
Figure 1. MPC9331 Logic Diagram
MPC9331 REVISION 7 March 11, 2016
2
©2016 Integrated Device Technology, Inc.
MPC9331 Data Sheet
3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR
REF_SEL
PLL_EN
18
FB_SEL
GND
V
CC
QB0
QB1
24
GND
QA1
QA0
V
CC
FSELA
FSELB
FSELC
NC
25
26
27
28
29
30
31
32
1
23
22
21
20
19
NC
17
16
15
14
GND
QC1
QC0
V
CC
FB_IN
CLK_STOP1
CLK_STOP0
NC
13
12
11
10
9
8
GND
Function
MPC9331
2
3
4
5
6
7
PWR_DN
OE/MR
CCLK
NC
PCKL
It is recommended to use an external RC filter for the analog V
CC_PLL
power supply pin. Please see
Applications Information
section for details.
Figure 2. MPC9331 32-Lead Package Pinout
(Top View)
Table 1. Pin Configuration
Pin
CCLK
PCLK, PCLK
FB_IN
FB_SEL
REF_SEL
PWR_DN
FSELA
FSELB
FSELC
PLL_EN
CLK_STOP0-1
OE/MR
QA0-1, QB0-1, QC0-1
GND
V
CC_PLL
V
CC
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Supply
Supply
Type
LVCMOS
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
CC
V
CC
PLL reference clock signal
Differential PECL reference clock signal
PLL feedback signal input, connect to an output
Feedback select
Reference clock select
Output frequency and power down select
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
PLL enable/disable
Clock output enable/disable
Output enable/disable (high-impedance tristate) and device reset
Clock outputs
Negative power supply (GND)
PLL positive power supply (analog power supply). It is recommended to use external RC filter
for the analog power supply pin V
CC_PLL.
Please see applications section for details.
Positive power supply for I/O and core. All V
CC
pins must be connected to the positive power
supply for correct operation
Supply
MPC9331 REVISION 7 March 11, 2016
V
CC_PLL
3
PCKL
©2016 Integrated Device Technology, Inc.
MPC9331 Data Sheet
3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR
Table 2. Function Table
Control
REF_SEL
FB_SEL
Default
0
1
0
PCLK is the PLL reference clock
Internal PLL feedback of 8. f
VCO
= 8 * f
ref
1
CCLK is the PLL reference clock
External feedback. Zero-delay operation
enabled for CCLK or PCLK as reference
clock
Normal operation mode with PLL enabled.
PLL_EN
1
Test mode with PLL disabled. The reference clock is
substituted for the internal VCO output. MPC9331 is fully static
and no minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
VCO
1 (High output frequency range)
Output divider
2
Output divider
2
Output divider
4
Outputs disabled (high-impedance state) and reset of the
device. During reset in external feedback configuration, the
PLL feedback loop is open. The VCO is tied to its lowest
frequency. The MPC9331 requires reset after any loss of PLL
lock. Loss of PLL lock may occur when the external feedback
path is interrupted. The length of the reset pulse should be
greater than one reference clock cycle (CCLK or PCLK). Reset
does not affect PLL lock in internal feedback configuration.
See
Table 3
PWR_DN
FSELA
FSELB
FSELC
OE/MR
1
0
0
0
1
VCO
2 (Low output frequency range)
Output divider
4
Output divider
4
Output divider
6
Outputs enabled (active)
CLK_STOP[0:1]
11
PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios.
See
Table 8
through
Table 10
for supported frequency ranges and output to input frequency ratios.
MPC9331 REVISION 7 March 11, 2016
4
©2016 Integrated Device Technology, Inc.
MPC9331 Data Sheet
Table 3. Clock Output Synchronous Disable (CLK_STOP) Function Table
(1)
CLK_STOP0
0
0
1
1
CLK_STOP1
0
1
0
1
QA[0:1]
Active
Active
Stopped in logic L state
Active
QB[0:1]
Stopped in logic L state
Stopped in logic L state
Stopped in logic L state
Active
3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR
QC[0:1]
Stopped in logic L state
Active
Active
Active
1. Output operation for OE/MR=1 (outputs enabled). OE/MR=0 will disable (high-impedance state) all outputs independent on CLK_STOP[0:1].
Table 4. General Specifications
Symbol
V
TT
MM
HBM
LU
C
PD
C
IN
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Power Dissipation Capacitance
Input Capacitance
200
2000
200
10
4.0
Min
Typ
V
CC
2
Max
Unit
V
V
V
mA
pF
pF
Per output
Inputs
Condition
Table 5. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.9
V
CC
+ 0.3
V
CC
+ 0.3
20
50
125
Unit
V
V
V
mA
mA
°C
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 6. DC Characteristics
(V
CC
= 3.3 V
5%, T
A
= 0°C to 70°C)
Symbol
V
IH
V
IL
V
PP
V
CMR(1)
V
OH
V
OL
Z
OUT
I
IN
I
CC_PLL
I
CCQ
Characteristics
Input high voltage
Input low voltage
Peak-to-peak input voltagePCLK, PCLK
Common Mode RangePCLK, PCLK
Output High Voltage
Output Low Voltage
Output impedance
Input Current
(3)
Maximum PLL Supply Current
Maximum Quiescent Supply Current
(4)
8.0
14 – 17
200
12
26
250
1.0
2.4
0.55
0.30
V
CC
– 0.6
Min
2.0
Typ
Max
V
CC
+ 0.3
0.8
Unit
V
V
mV
V
V
V
V
W
A
mA
mA
V
IN
= V
CC
or GND
V
CC_PLL
Pin
All V
CC
Pins
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
I
OH
= –24 mA
(2)
I
OL
= 24 mA
I
OL
= 12 mA
1. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
(DC) specification.
2. The MPC9331 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
series terminated transmission lines.
3. Inputs have pull-down or pull-up resistors affecting the input current.
4. OE/MR=0 (outputs in high-impedance state).
MPC9331 REVISION 7 March 11, 2016
5
©2016 Integrated Device Technology, Inc.
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