SP74HC132J datasheet, PDF - EEWORLD Datasheet

SP74HC132J: DescriptionNAND Gate, CMOS, CDIP14; Categorylogic logic; File Size130KB，2 Pages; ManufacturerSemi Processes Inc

Download Datasheet Parametric View All

SP74HC132J Overview

NAND Gate, CMOS, CDIP14

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	100767344
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknown
JESD-30 code	R-XDIP-T14
JESD-609 code	e0
Logic integrated circuit type	NAND GATE
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	2/6 V
Certification status	Not Qualified
Schmitt trigger	YES
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components