PI7C9X20303SL
PCI EXPRESS® PACKET SWITCH
DATASHEET
REVISION 1.1
July 2009
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PI7C9X20303SL
3Port-3Lane PCI Express® Switch
SlimLine
TM
Family
Datasheet
DISCLAIMER
The information contained in this document is proprietary and confidential to Pericom Semiconductor Cooperation (PSC). No part of this
document may be copied or reproduced in any form or by any means without prior written consent of PSC.
The information in this document is subjected to change without notice.
PSC retains the right to make changes to this document at any time
without notice. While the information contained in this document has been checked for accuracy, such information is preliminary, and PSC does
not warrant the accuracy and completeness of such information. PSC does not assume any liability or responsibility for damages arising from any
use of the information contained in this document.
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a
specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.
1)
Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant injury to the user.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to
make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best
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2)
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Page 2 of 76
July 2009 – Revision 1.1
Pericom Semiconductor
PI7C9X20303SL
3Port-3Lane PCI Express® Switch
SlimLine
TM
Family
Datasheet
REVISION HISTORY
Date
9/13/07
10/04/07
Revision Number
0.1
0.2
Description
Drafted Preliminary Datasheet
Corrected Chapter 3 Pin Description (DTX’s and DEQ’s default values)
Updated Chapter 3.5 JTAG Signals description
Updated Chapter 7.2.53 bit
Remove VDDP, VDDAUX from Chapter 10 Power Management and
Chapter 11.1 Absolute Maximum Ratings
Revised Chapter 10 Power Management
Corrected Chapter 3 Pin Description (PERP/PERN, PETP/PETN,
WAKEUP_L, SLOT_IMP, SLOTCLK, EEPD, SMBDATA, SCAN_EN,
PORTACT to PORTERR, DTX, DEQ)
Updated 5.1 Physical Layer Circuit and Chapter 5.6 Queue
Updated Disclaimer
Corrected Chapter 2 General Description
Updated Chapter 13 Ordering Information
Corrected Chapter 3 Pin Description (DWNRST_L, SLOT_IMP,
PORTERR, NC)
Corrected Chapter 4 Pin Assignment (DWNRST_L[3], SLOT_IMP[3],
PORTERR[3])
Removed Virtual Channel 1 related information in Chapter 2 General
Description and Chapter 5 (5.5 TC/VC Mapping, 5.6 Queue, 5.7 Transaction
Ordering, 5.9 VC Arbitration)
Updated Footer
Updated Chapter 5.8 Port Arbitration
Updated Chapter 6.1.3 EEPROM Space Address Map
Added Chapter 6.2 SMBus
Fixed Chapter 6.1.4 Mapping EEPROM table format
Updated Chapter 7 Registers (Offset 08h, 100h, 140h to 1BCh, B0h bit 31)
Updated Chapter 6 EEPROM (50h, 52h, 54h Reserved)
Updated 7.2.91 [7:0] (Removed VC1 description)
Corrected Chapter 5 Functional Description (multiple virtual channels)
Updated Chapter 6 EEPROM (0Ch)
Modified Chapter 7 Registers (7.2.2 Device ID Register, 7.2.50 Bit[13:15]
Replay Time-Out Counter, 7.2.52 Bit[14:15] Switch Operation Mode, 7.2.64
PCI Express Capability Bit[24], 7.2.70 Link Status Bit[28], 7.2.99 Power
Budgeting Data, 7.2.100 Power Budget Capability)
Updated 9.5 JTAG Boundary Scan Register Order
Updated Chapter 3.5 Power Pins (VDDC, VDDA, VDDAUX, VTT)
Updated Chapter 6 EEPROM (A0h, A2h, A4h)
Updated Chapter 1 Features (Power Dissipation)
Updated Chapter 11.1 AC Specification (VDDAUX)
Updated Chapter 11.2 DC Specification (Power Consumption, VDDAUX)
Updated Chapter 10 Power Management (VDDAUX)
Updated 1 Features (typical latency, removed peer-to-peer switching, power
consumption)
Updated Chapter 3.1 PCI Express Interface Signals (REFCLKP, REFCLKN,
PRSNT)
Updated Chapter 4.1 PIN List of 128-PIN LQFP (PRSNT)
Modified 5.1 Physical Layer Circuit
Updated Chapter 6.1.3 EEPROM Space Address Map (10h to 14h, 50h to
54h)
Modified 6.1.4 Mapping EEPROM Contents To Configuration Registers
(0Ch: Ordering Frozen, TX SOF Latency, Surprise Down Capability Enable,
Power Management Data Select, 20h, 22h, 24h: Removed LPVC, Added
PMCSR, 51h, 52h, 53h, 54h, 55h, 56h)
Updated Chapter 7.2 Transparent Mode Configuration Registers (A4h, B4h,
10/31/07
0.3
2/20/08
0.4
5/28/08
0.5
Page 3 of 76
July 2009 – Revision 1.1
Pericom Semiconductor
PI7C9X20303SL
3Port-3Lane PCI Express® Switch
SlimLine
TM
Family
Datasheet
B8, BCh, C0h, C4h)
Updated 7.2.5 Revision ID Register, 7.2.27 Interrupt Pin Register, 7.2.32
Power Management Data Register Bit[3], 7.2.46 Next Item Pointer Register,
7.2.50 Replay Time-Out Counter, 7.2.51 Acknowledge Latency Timer,
7.5.52 Switch Operation Mode, 7.2.53 Switch Operation Mode
(Downstream Port) Bit[16:31], 7.2.54 XPIP CSR2, 7.2.55 SSID/SSVID
Capability ID Register, 7.2.56 Next Item Pointer Register, 7.2.57 Subsystem
Vendor ID Register, 7.2.58 Subsystem ID Register, 7.2.65 PCI Express
Capabilities Register Bit[19:16], 7.2.69 Link Capabilities Register Bit 19,
7.2.86 Capability Version Bit[19:16], 7.2.93 VC Resource Control Register
Bit [26:24], 7.2.97 Capability Version Bit[19:16]
Modified 1. Features
Modified 3.3 Miscellaneous Signals (DEQ[3] to P0_CTCDIS, HIDRV to
P1_CTCDIS, LODRV to P2_CTCDIS, DTX[3] to TEST7)
Modified 4.1 Pin List (DEQ[3] to P0_CTCDIS, HIDRV to P1_CTCDIS,
LODRV to P2_CTCDIS[2], DTX[3] to TEST7)
Modified 6.1.4 Mapping EEPROM Contents To Configuration Registers
(0Ch, 10h, 12h, 14h)
Corrected 7.2.27 Interrupt Pin Register
Added 7.2.55 TL CSR
Modified 11.2 Power Consumption
Updated Chapter 1 Features (updated Industrial Temperature Range)
Updated Section 11.1 Absolute Maximum Ratings: Ambient Temperature
with power applied
Updated Figure 12-1 Package outline drawing
Updated Chapter 1 Features (power dissipation)
Modified 11.2 Power Consumption
Corrected Chapter 7.2 (8Ch - Next Item Pointer)
Updated Figure 12-1 Package outline drawing
Updated Chapter 13 Ordering Information
Removed “Preliminary” and “Confidential” references
Updated Chapter 3.2 Port Configuration Signals (PRSNT, SLOTCLK)
Updated Chapter 3.3 Miscellaneous Signals (updated PWR_SAV pin,
SMBCLK, SMBDATA, PWR_SAV, CTCDIS, EEPD)
Updated Chapter 3.4 JTAG Boundary Scan Signals (TMS, TDI, TRST_L)
Updated Chapter 7.2.52 Switch Operation Mode (Bit[31:16])
Updated Chapter 13 Ordering Information
7/10/08
0.6
9/5/08
0.7
10/3/08
11/24/08
0.8
1.0
7/20/09
1.1
Page 4 of 76
July 2009 – Revision 1.1
Pericom Semiconductor
PI7C9X20303SL
3Port-3Lane PCI Express® Switch
SlimLine
TM
Family
Datasheet
TABLE OF CONTENTS
1
2
3
FEATURES.........................................................................................................................................................10
GENERAL DESCRIPTION..............................................................................................................................11
PIN DESCRIPTION...........................................................................................................................................12
3.1
3.2
3.3
3.4
3.5
4
4.1
5
PCI EXPRESS INTERFACE SIGNALS ....................................................................................................12
PORT CONFIGURATION SIGNALS .......................................................................................................12
MISCELLANEOUS SIGNALS..................................................................................................................12
JTAG BOUNDARY SCAN SIGNALS ......................................................................................................13
POWER PINS.............................................................................................................................................14
PIN LIST
OF
128-PIN LQFP.......................................................................................................................15
PIN ASSIGNMENTS .........................................................................................................................................15
FUNCTIONAL DESCRIPTION.......................................................................................................................16
5.1
PHYSICAL LAYER CIRCUIT ..................................................................................................................16
5.2
DATA LINK LAYER (DLL)......................................................................................................................18
5.3
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ..............................................18
5.4
ROUTING ..................................................................................................................................................18
5.5
TC/VC MAPPING......................................................................................................................................19
5.6
QUEUE.......................................................................................................................................................19
5.6.1
PH .......................................................................................................................................................19
5.6.2
PD .......................................................................................................................................................19
5.6.3
NPHD .................................................................................................................................................19
5.6.4
CPLH ..................................................................................................................................................19
5.6.5
CPLD ..................................................................................................................................................19
5.7
TRANSACTION ORDERING...................................................................................................................20
5.8
PORT ARBITRATION ..............................................................................................................................20
5.9
FLOW CONTROL .....................................................................................................................................21
5.10 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) .............................................21
6
EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS..................................................................22
6.1
EEPROM INTERFACE .............................................................................................................................22
6.1.1
AUTO MODE EERPOM ACCESS .....................................................................................................22
6.1.2
EEPROM MODE AT RESET..............................................................................................................22
6.1.3
EEPROM SPACE ADDRESS MAP ....................................................................................................22
6.1.4
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS..........................................24
6.2
SMB
US
INTERFACE .................................................................................................................................29
7
REGISTER DESCRIPTION.............................................................................................................................30
7.1
REGISTER TYPES ....................................................................................................................................30
7.2
TRANSPARENT MODE CONFIGURATION REGISTERS ....................................................................30
7.2.1
VENDOR ID REGISTER – OFFSET 00h ...........................................................................................32
7.2.2
DEVICE ID REGISTER – OFFSET 00h.............................................................................................32
7.2.3
COMMAND REGISTER – OFFSET 04h............................................................................................32
7.2.4
PRIMARY STATUS REGISTER – OFFSET 04h.................................................................................33
7.2.5
REVISION ID REGISTER – OFFSET 08h .........................................................................................33
7.2.6
CLASS CODE REGISTER – OFFSET 08h .........................................................................................33
7.2.7
CACHE LINE REGISTER – OFFSET 0Ch.........................................................................................34
Page 5 of 76
July 2009 – Revision 1.1
Pericom Semiconductor
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