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IS61NLP51236B-200TQLI

Description
sram 18mb, 200mhz 512k x 36 sync sram
Categorysemiconductor    Other integrated circuit (IC)   
File Size2MB,39 Pages
ManufacturerAll Sensors
Environmental Compliance
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IS61NLP51236B-200TQLI Overview

sram 18mb, 200mhz 512k x 36 sync sram

IS61NLP51236B-200TQLI Parametric

Parameter NameAttribute value
ManufactureISSI
Product CategorySRAM
RoHSYes
Memory Size18 Mbi
Organizati512 k x 36
Access Time3 ns
Supply Voltage - Max3.465 V
Supply Voltage - Mi3.135 V
Maximum Operating Curre240 mA
Maximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 C
Mounting StyleSMD/SMT
Package / CaseQFP-100
Maximum Clock Frequency200 MHz
Memory TypeSynchronous SRAM
IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B
IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B
512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS
SYNCHRONOUS SRAM
JULY 2014
FEATURES
100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address, data and
control
Interleaved or linear burst sequence control
using MODE input
Three chip enables for simple depth
expansion and address pipelining
Power Down mode
Common data inputs and data outputs
/CKE pin to enable clock and suspend
operation
JEDEC 100-pin QFP, 165-ball BGA and 119-
ball BGA packages
Power supply:
NLP: V
DD
3.3V (± 5%), V
DDQ
3.3V/2.5V (± 5%)
NVP: V
DD
2.5V (± 5%), V
DDQ
2.5V (± 5%)
NVVP: V
DD
1.8V (± 5%), V
DDQ
1.8V (± 5%)
JTAG Boundary Scan for BGA packages
Commercial, Industrial and Automotive (x36)
temperature support
Lead-free available
For leaded option, please contact ISSI.
DESCRIPTION
The 18Meg product family features high-speed,
low-power synchronous static RAMs designed to
provide a burstable, high-performance, 'no wait'
state, device for networking and communications
applications. They are organized as 512K words
by 36 bits and 1024K words by 18 bits, fabricated
with
ISSI's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles
are eliminated when the bus switches from read
to write, or write to read. This device integrates a
2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single
monolithic circuit.
All synchronous inputs pass through registers are
controlled by a positive-edge-triggered single
clock input. Operations may be suspended and all
synchronous inputs ignored when Clock Enable,
/CKE is HIGH. In this state the internal device will
hold their previous values.
All Read, Write and Deselect cycles are initiated
by the ADV input. When the ADV is HIGH the
internal burst counter is incremented. New
external addresses can be loaded when ADV is
LOW.
Write cycles are internally self-timed and are
initiated by the rising edge of the clock inputs and
when /WE is LOW. Separate byte enables allow
individual bytes to be written.
A burst mode pin (MODE) defines the order of the
burst sequence. When tied HIGH, the interleaved
burst sequence is selected. When tied LOW, the
linear burst sequence is selected.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle time
Frequency
-250
2.6
4
250
-200
3.0
5
200
Units
ns
ns
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at
any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein.
Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders
for products.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
7/11/2014
1

IS61NLP51236B-200TQLI Related Products

IS61NLP51236B-200TQLI IS61NLP51236B-200B3LI IS61NLP51236B-200B3LI-TR IS61NLP51236B-200TQLI-TR
Description sram 18mb, 200mhz 512k x 36 sync sram sram 18mb, 200mhz 512k x 36 sync sram sram 18mb, 200mhz 512k x 36 sync sram sram 18mb 200mhz 512k x 36 sync sram
Manufacture ISSI ISSI ISSI ISSI
Product Category SRAM SRAM SRAM SRAM
RoHS Yes Yes Yes Yes
Memory Size 18 Mbi 18 Mbi 18 Mbi 18 Mbi
Organizati 512 k x 36 512 k x 36 512 k x 36 512 k x 36
Access Time 3 ns 3 ns 3 ns 3 ns
Supply Voltage - Max 3.465 V 3.465 V 3.465 V 3.465 V
Supply Voltage - Mi 3.135 V 3.135 V 3.135 V 3.135 V
Maximum Operating Curre 240 mA 240 mA 240 mA 240 mA
Maximum Operating Temperature + 85 C + 85 C + 85 C + 85 C
Minimum Operating Temperature - 40 C - 40 C - 40 C - 40 C
Mounting Style SMD/SMT SMD/SMT SMD/SMT SMD/SMT
Package / Case QFP-100 BGA-165 BGA-165 QFP-100
Maximum Clock Frequency 200 MHz 200 MHz 200 MHz 200 MHz
Memory Type Synchronous SRAM Synchronous SRAM Synchronous SRAM Synchronous SRAM
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