PI6C557-03A
PCIe 2.0 Clock Generator with 2 HCSL Outputs
Features
ÎÎ
PCIe® 2.0 compliant
Description
The PI6C557-03A is a spread spectrum clock generator compli-
ant to PCI Express® 2.0 and Ethernet requirements. The device is
used for PC or embedded systems to substantially reduce Electro-
magnetic Interference (EMI).
The PI6C557-03A provides two differential (HCSL) or LVDS
spread spectrum outputs. The PI6C557-03A is configured to se-
lect spread and clock selection. Using Pericom's patented Phase-
Locked Loop (PLL) techniques, the device takes a 25MHz crystal
input and produces two pairs of differential outputs (HCSL) at
25MHz, 100MHz, 125MHz and 200MHz clock frequencies. It
also provides spread selection of -0.5%, -0.75%, and no spread.
à
Phase jitter - 2.1ps RMS (typ)
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LVDS compatible outputs
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Supply voltage of 3.3V ±10%
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25MHz crystal or clock input frequency
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HCSL outputs, 0.8V Current mode differential pair
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Jitter 35ps cycle-to-cycle (typ)
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Spread of -0.5%, -0.75%, and no spread
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Industrial temperature range
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Spread Bypass option available
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Spread and frequency selection via external pins
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Packaging: (Pb-free and Green)
à
à
16-pin TSSOP (L16)
16-pin QSOP (Q16)
Block Diagram
Pin Configuration (16-Pin TSSOP)
VDD
2
SS1:SS0
S1:S0
2
2
CLK0
Control
Logic
CLK0
S0
S1
SS0
X1/CLK
X2
OE
GNDX
SS1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDX
CLK0
CLK0
GNDA
VDDA
CLK1
CLK1
IREF
Phase
Lock
Loop
CLK1
CLK1
X1/CLK
25 MHz
crystal or clock X2
Pulling
Capacitors
Crystal
Driver
2
GND
OE
R
R
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13-0052
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PI6C557-03A
Rev.E
05/06/13
PCIe 2.0 Clock Generator with 2 HCSL Outputs
Pin Description
Pin # Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S0
S1
SS0
X1/CLK
X2
OE
GNDX
SS1
IREF
CLK1
CLK1
VDDA
GNDA
CLK0
CLK0
VDDX
PI6C557-03A
I/O Type
Input
Input
Input
Input
Output
Input
Power
Input
Output
Output
Output
Power
Power
Output
Output
Power
Description
Select pin 0 (Internal pull-up resistor). See Table 1.
Select pin 1 (Internal pull-up resistor). See Table 1.
Spread Select pin 0 (Internal pull-up resistor). See Table 2.
Crystal or clock input. Connect to a 25MHz crystal or single ended clock.
Crystal connection. Leave unconnected for clock input.
Output enable. Internal pull-up resistor.
Crystal ground pin.
Spread Select pin 1 (Internal pull-up resistor). See Table 2.
Precision resistor attached to this pin is connected to the internal current reference.
HCSL compliment clock output
HCSL clock output
Connect to a +3.3V source.
Output and analog circuit ground.
HCSL compliment clock output
HCSL clock output
Connect to a +3.3V source.
Table 1: Output Frequency Select Table
S1
0
0
1
1
S0
0
1
0
1
CLK(MHz)
25
100
125
200
Table 2: Spread Selection Table
SS1
0
0
1
1
SS0
0
1
0
1
Spread
No Spread
Down -0.5
Down -0.75
No Spread
All trademarks are property of their respective owners.
13-0052
2
www.pericom.com
PI6C557-03A
Rev.E
05/06/13
PCIe 2.0 Clock Generator with 2 HCSL Outputs
Application Information
Decoupling Capacitors
Decoupling capacitors of 0.01μF should be connected between
each V
DD
pin and the ground plane and placed as close to the
V
DD
pin as possible.
Crystal
Use a 25MHz fundamental mode parallel resonant crystal with
less than 300PPM of error across temperature.
Crystal Capacitors
C
L
= Crystals's load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 8) *2
For example, for a crystal with 16pF load caps, the external ef-
fective crystal cap would be 16 pF. (16-8)*2=16.
Current Source (IREF) Reference Resistor - R
R
If board target trace impedance is 50Ω,
then R
R
= 475Ω providing an IREF of 2.32 mA. The output cur-
rent (I
OH
) is 6*IREF.
Output Termination
The PCI Express differential clock outputs of the PI6C557-03A
are open source drivers and require an external series resistor
and a resistor to ground. These resistor values and their allow-
able locations are shown in detail in the PCI Express Layout
Guidelines section.
The PI6C557-03A can be configured for LVDS compatible volt-
age levels. See the LVDS Compatible Layout Guidelines section.
R
R
=475
Ω
See Output Termination
Sections
IREF =2.3mA
6*IREF
PI6C557-03A
Output Structures
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13-0052
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PI6C557-03A
Rev.E
05/06/13
PCIe 2.0 Clock Generator with 2 HCSL Outputs
PCI Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50Ω trace.
L2 length, route as non-coupled 50Ω trace.
L3 length, route as non-coupled 50Ω trace.
R
S
R
T
PI6C557-03A
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Unit
inch
inch
inch
Ω
Ω
Differential Routing on a Single PCB
L4 length, route as coupled microstrip 100Ω differential trace.
L4 length, route as coupled stripline 100Ω differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit
inch
inch
Differential Routing to a PCI Express connector
L4 length, route as coupled microstrip 100Ω differential trace.
L4 length, route as coupled stripline 100Ω differential trace.
Dimension or Value
0.25 min to 14 max
0.225 min to 12.6 max
Unit
inch
inch
PCI Express Device Routing
L1
L1’
R
S
R
S
L2
L2’
R
T
L3’
R
T
L3
L4
L4’
PI6C557-03A
Output
Clock
PCI-Express
Load or
Connector
Typical PCI Express (HCSL) Waveform
800 mV
0
t
OR
0.52 V
0.175 V
250 ps
400 ps
t
OF
0.52 V
0.175 V
All trademarks are property of their respective owners.
13-0052
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www.pericom.com
PI6C557-03A
Rev.E
05/06/13
PCIe 2.0 Clock Generator with 2 HCSL Outputs
Application Information
LVDS Recommendations for Differential Routing
L1 length, route as non-coupled 50Ω trace.
L2 length, route as non-coupled 50Ω trace.
RP
RQ
RT
L3 length, route as 100Ω differential trace.
L3 length, route as 100Ω differential trace.
PI6C557-03A
Dimension or Value
0.5 max
0.2 max
100
100
150
Unit
inch
inch
Ω
Ω
Ω
LVDS Device Routing
L1
L1’
R
S
R
S
L2
L2’
R
T
L3’
R
T
L3
L4
L4’
PI6C557-03A
Output
Clock
PCI-Express
Load or
Connector
All trademarks are property of their respective owners.
13-0052
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PI6C557-03A
Rev.E
05/06/13
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