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IS61LPS12836A-250TQL-TR

Description
sram 4M 3.3V 250mhz 128kx36 sync sram
Categorysemiconductor    Other integrated circuit (IC)   
File Size498KB,26 Pages
ManufacturerAll Sensors
Environmental Compliance  
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IS61LPS12836A-250TQL-TR Overview

sram 4M 3.3V 250mhz 128kx36 sync sram

IS61LPS12836A-250TQL-TR Parametric

Parameter NameAttribute value
ManufactureISSI
Product CategorySRAM
RoHSYes
Memory Size4 Mbi
Access Time2.6 ns
Supply Voltage - Max3.465 V
Supply Voltage - Mi3.135 V
Maximum Operating Curre225 mA
Maximum Operating Temperature+ 70 C
Minimum Operating Temperature0 C
Mounting StyleSMD/SMT
Package / CaseTQFP-100
PackagingReel
Maximum Clock Frequency250 MHz
Factory Pack Quantity800
TypeSynchronous
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
128K x 32, 128K x 36, 256K x 18
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth ex-
pansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LPS: V
dd
3.3V + 5%,
V
ddq
3.3V/2.5V + 5%
VPS: V
dd
2.5V + 5%,
V
ddq
2.5V + 5%
• JEDEC 100-Pin QFP, 119-ball and 165-ball
BGA packages
• Automotive temperature available
• Lead Free available
DECEMBER 2013
4 Mb SYNCHRONOUS PIPELINED, SINgLE CYCLE DESELECT STATIC RAM
DESCRIPTION
The
ISSI
IS61(64)LPS12832A, IS61(64)LPS/VP-
S12836A and IS61(64)LPS/VPS25618A are
high-speed,
low-power synchronous static
RAMs
designed to provide
burstable, high-performance memory for communication
and networking applications. The IS61(64)LPS12832A
is
organized as 131,072 words by 32 bits.
The IS61(64)LPS/
VPS12836A is organized as 131,072 words by 36 bits.
The IS61(64)LPS/VPS25618A
is organized as 262,144
words by 18 bits. Fabricated with
ISSI
's advanced CMOS
technology, the device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx).
In addition, Global
Write (GW)
is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence or-
der, Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH
or left floating.
FAST ACCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
250
2.6
4
250
200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil-
ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. H1
12/06/2013
1

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Description sram 4M 3.3V 250mhz 128kx36 sync sram sram 4M (128kx36) 200mhz sync sram 3.3v sram 4M (128kx32) 200mhz sync sram 3.3v sram 4mb 256kx18 200mhz sync sram 3.3v sram 4mb 256kx18 200mhz sync sram 3.3v sram 4mb 128kx36 200mhz sync sram 3.3v sram 4M (256kx18) 200mhz sync sram 3.3v sram 4mb 128kx36 200mhz sync sram 3.3v sram 4M (128kx32) 200mhz sync sram 3.3v sram 4M 3.3V 250mhz 128kx36 sync sram
Manufacture ISSI ISSI ISSI ISSI ISSI ISSI ISSI ISSI ISSI ISSI
Product Category SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM
RoHS Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Memory Size 4 Mbi 4 Mbi 4 Mbi 4 Mbi 4 Mbi 4 Mbi 4 Mbi 4 Mbi 4 Mbi 4 Mbi
Access Time 2.6 ns 3.1 ns 3.1 ns 3.1 ns 3.1 ns 3.1 ns 3.1 ns 3.1 ns 3.1 ns 2.6 ns
Supply Voltage - Max 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V
Supply Voltage - Mi 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
Maximum Operating Curre 225 mA 210 mA 225 mA 210 mA 210 mA 210 mA 200 mA 210 mA 225 mA 225 mA
Maximum Operating Temperature + 70 C + 85 C + 125 C + 85 C + 85 C + 85 C + 70 C + 85 C + 125 C + 70 C
Minimum Operating Temperature 0 C - 40 C - 40 C - 40 C - 40 C - 40 C 0 C - 40 C - 40 C 0 C
Mounting Style SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT SMD/SMT
Package / Case TQFP-100 BGA TQFP-100 TQFP-100 TQFP-100 TQFP-100 BGA TQFP-100 TQFP-100 TQFP-100
Packaging Reel Reel Reel Tube Reel Reel Reel Tube Tray Tray
Maximum Clock Frequency 250 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 250 MHz
Factory Pack Quantity 800 1000 800 72 800 800 1000 72 72 72
Type Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous
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