TC74HC123AP/AF
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74HC123AP,TC74HC123AF
Dual Retriggerable Monostable Multivibrator
The TC74HC123A is a high speed CMOS MONOSTABLE
MULTIVIBRATOR fabricated with silicon gate C
2
MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
There are two trigger inputs,
A input (negative edge), and B
input (positive edge). These inputs are valid for a slow rise/fall
time signal (tr = tf = 1 s) as they are schmitt trigger inputs. This
device may also be triggered by using
CLR
input (positive
edge).
After triggering, the output stays in a MONOSTABLE state for
a time period determined by the external resistor and capacitor
(Rx, Cx ). A low level at the
CLR
input breaks this state. In the
MONOSTABLE state, if a new trigger is applied, it extends the
MONOSTABLE period (retrigger mode).
Limits for Cx and Rx are:
External capacitor, Cx: No limit
External resistor, Rx: V
CC
= 2.0 V more than 5 kΩ
V
CC
≥
3.0 V more than 1 kΩ
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
TC74HC123AP
TC74HC123AF
Features (Note)
•
•
High speed: t
pd
= 25 ns (typ.) at V
CC
= 5 V
Low power dissipation
Standby state: I
CC
= 4
μ
A (max) at Ta = 25°C
Active state: I
CC
= 700
μ
A (max) at Ta = 25°C
High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
Output drive capability: 10 LSTTL loads
Symmetrical output impedance: |I
OH
| = I
OL
= 4 mA (min)
∼
Balanced propagation delays: t
pLH
−
t
pHL
Wide operating voltage range: V
CC
(opr) = 2 to 6 V
Pin and function compatible with 74LS123
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
: 1.00 g (typ.)
: 0.18 g (typ.)
•
•
•
•
•
•
Note:
In the case of using only one circuit,
CLR
should be tied to GND, Rx/Cx
½
Cx
½
Q
½
Q
should be tied to
OPEN, the other inputs should be tied to V
CC
or GND.
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TC74HC123AP/AF
Pin Assignment
IEC Logic Symbol
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TC74HC123AP/AF
Block Diagram (Note 1)(Note 2)
Note 1: Cx, Rx, Dx are external
capacitor, resistor, and diode, respectively.
Note 2: External clamping diode, Dx;
The external capacitor is charged to V
CC
level in the wait state, i.e. when no trigger is applied.
If the supply voltage is turned off, Cx is discharges mainly through the internal (parasitic) diode. If Cx is
sufficiently large and V
CC
drops rapidly, there will be some possibility of damaging the IC through in rush
current or latch-up. If the capacitance of the supply voltage filter is large enough and V
CC
drops slowly, the
in rush current is automatically limited and damage to the IC is avoided.
The maximum value of forward current through the parasitic diode is
±20
mA.
In the case of a large Cx, the limit of fall time of the supply voltage is determined as follows:
t
f
≥
(V
CC
−
0.7) Cx/20 mA
(tf is the time between the supply voltage turn off and the supply voltage reaching 0.4 V
CC
.)
In the event a system does not satisfy the above condition, an external clamping diode (Dx) is needed to
protect the IC from in rush current.
Truth Table
Inputs
A
Outputs
CLR
B
H
Q
Q
Function
Output Enable
H
H
H
H
L
L
H
H
X
H
L
L
X
L
X
Inhibit
Inhibit
Output Enable
Output Enable
H
X
L
L
H
Inhibit
X: Don’t care
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TC74HC123AP/AF
System Diagram
V
CC
V
ref
L
V
ref
H
Q
P
C
1
C
2
R
X
/C
X
Q
N
V
CC
D R
Q
C
X
F/F
A
B
CK
Q
Q
Q
CLR
Timing Chart
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TC74HC123AP/AF
Functional Description
(1)
Stand-by state
The external capacitor (Cx) is fully charged to V
CC
in the stand-by state. That means, before
triggering, the Q
P
and Q
N
transistors which are connected to the Rx/Cx node are in the off state. Two
comparators that relate to the timing of the output pulse, and two reference voltage supplies turn off.
The total supply current is only leakage current.
Trigger operation
Trigger operation is effective in any of the following three cases. First, the condition where the
A
input is low, and the B input has a rising signal; second, where the B input is high, and the A input
has a falling signal; and third, where the A input is low and the B input is high, and the
CLR
input has a rising signal.
After a trigger becomes effective, comparators C1 and C2 start operating, and Q
N
is turned on. The
external capacitor discharges through Q
N
. The voltage level at the Rx/Cx node drops. If the Rx/Cx
voltage level falls to the internal reference voltage Vref L, the output of C1 becomes low. The flip-flop
is then reset and Q
N
turns off. At that moment C1 stops but C2 continues operating.
After Q
N
turns off, the voltage at the Rx/Cx node starts rising at a rate determined by the time
constant of external capacitor Cx and resistor Rx.
Upon triggering, output Q becomes high, following some delay time of the internal F/F and gates. It
stays high even if the voltage of Rx/Cx changes from falling to rising. When Rx/Cx reaches the
internal reference voltage Vref H, the output of C2 becomes low, the output Q goes low and C2 stops
its operation. That means, after triggering, when the voltage level of the Rx/Cx node reaches Vref H,
the IC returns to its MONOSTABLE state.
With large values of Cx and Rx, and ignoring the discharge time of the capacitor and internal
delays of the IC, the width of the output pulse, tw (OUT), is as follows:
tw (OUT)
=
1.0 Cx Rx
Retrigger operation
When a new trigger is applied to either input A or B while in the MONOSTABLE state, it is
effective only if the IC is charging Cx. The voltage level of the Rx/Cx node then falls to Vref L level
again. Therefore the Q output stays high if the next trigger comes in before the time period set by Cx
and Rx.
If the new trigger is very close to previous trigger, such as an occurrence during the discharge cycle,
it will have no effect.
The minimum time for a trigger to be effective 2nd trigger, trr (Min.), depends on V
CC
and Cx.
Reset operation
In normal operation, the
CLR
input is held high. If
CLR
is low, a trigger has no effect because
the Q output is held low and the trigger control F/F is reset. Also, Q
P
turns on and Cx is charged
rapidly to V
CC
.
This means if
CLR
is set low, the IC goes into a wait state.
(2)
(3)
(4)
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