C8051T630/1/2/3/4/5
Mixed-Signal Byte-Programmable EPROM MCU
Analog Peripherals
-
10-Bit ADC (‘T630/2/4 only)
•
•
•
•
•
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
Up to 500 ksps
Up to 16 external inputs
VREF from on-chip VREF, external pin,
Internal Regulator or V
DD
Internal or external start of conversion source
Built-in temperature sensor
-
-
10-Bit Current Output DAC (‘T630/2/4 only)
Comparator
•
•
•
Memory
-
768 Bytes internal data RAM (256 + 512)
-
8, 4, or 2 kB byte-programmable EPROM code
memory
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (<0.5 µA)
On-Chip Debug
-
C8051F336 can be used as code development
-
-
platform; Complete development kit available
On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug
Provides breakpoints, single stepping,
inspect/modify memory and registers
Digital Peripherals
-
17 Port I/O with high sink current capability
-
Hardware enhanced UART, SMBus™, and
-
-
enhanced SPI™ serial ports
Four general purpose 16-bit counter/timers
•
Timer 3 supports real-time clock using external clock
source
Supply Voltage 1.8 to 3.6 V
-
On-chip LDO for internal core supply
-
Built-in voltage supply monitor
Temperature Range: –40 to +85 °C
16-Bit programmable counter array (PCA) with three
capture/compare modules and enhanced PWM
functionality
Clock Sources
-
Two internal oscillators:
•
•
24.5 MHz with ±2% accuracy supports crystal-less
UART operation and low-power suspend mode with
fast wake time
80/40/20/10 kHz low frequency, low power operation
-
-
External oscillator: RC, C, or CMOS Clock
Can switch between clock sources on-the-fly; useful
in power saving modes
20-Pin QFN Package (4x4 mm)
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CROSSBAR
Port 0
10-bit
500 ksps
ADC
VREF
10-bit
Current
DAC
+
Port 1
P2.0
TEMP
SENSOR
-
VOLTAGE
COMPARATOR
‘T630/2/4 Only
24.5 MHz PRECISION
INTERNAL OSCILLATOR
LOW FREQUENCY INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
2/4/8 kB
EPROM
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
768 B SRAM
POR
WDT
Rev. 1.0 1/09
Copyright © 2009 by Silicon Laboratories
C8051T630/1/2/3/4/5
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
C8051T630/1/2/3/4/5
2
Rev. 1.0
C8051T630/1/2/3/4/5
Table of Contents
1. System Overview ..................................................................................................... 15
2. Ordering Information ............................................................................................... 17
3. Pin Definitions.......................................................................................................... 18
4. QFN-20 Package Specifications ............................................................................. 21
5. Electrical Characteristics ........................................................................................ 23
5.1. Absolute Maximum Specifications..................................................................... 23
5.2. Electrical Characteristics ................................................................................... 24
5.3. Typical Performance Curves ............................................................................. 32
6. 10-Bit ADC (ADC0, C8051T630/2/4 only)................................................................ 33
6.1. Output Code Formatting .................................................................................... 34
6.2. 8-Bit Mode ......................................................................................................... 34
6.3. Modes of Operation ........................................................................................... 34
6.3.1. Starting a Conversion................................................................................ 34
6.3.2. Tracking Modes......................................................................................... 35
6.3.3. Settling Time Requirements...................................................................... 36
6.4. Programmable Window Detector....................................................................... 40
6.4.1. Window Detector Example........................................................................ 42
6.5. ADC0 Analog Multiplexer (C8051T630/2/4 only)............................................... 43
7. Temperature Sensor (C8051T630/2/4 only) ........................................................... 45
7.1. Calibration ......................................................................................................... 45
8. 10-Bit Current Mode DAC (IDA0, C8051T630/2/4 only) ......................................... 48
8.1. IDA0 Output Scheduling .................................................................................... 48
8.1.1. Update Output On-Demand ...................................................................... 48
8.1.2. Update Output Based on Timer Overflow ................................................. 49
8.1.3. Update Output Based on CNVSTR Edge ................................................. 49
8.2. IDAC Output Mapping ....................................................................................... 49
9. Voltage Reference Options ..................................................................................... 52
10. Voltage Regulator (REG0) ..................................................................................... 55
11. Comparator0........................................................................................................... 57
11.1. Comparator Multiplexer ................................................................................... 61
12. CIP-51 Microcontroller........................................................................................... 63
12.1. Instruction Set.................................................................................................. 64
12.1.1. Instruction and CPU Timing .................................................................... 64
12.2. CIP-51 Register Descriptions .......................................................................... 69
13. Memory Organization ............................................................................................ 72
13.1. Program Memory............................................................................................. 73
13.2. Data Memory ................................................................................................... 73
13.2.1. Internal RAM ........................................................................................... 73
13.2.1.1. General Purpose Registers ............................................................ 74
13.2.1.2. Bit Addressable Locations .............................................................. 74
13.2.1.3. Stack ............................................................................................ 74
13.2.2. External RAM .......................................................................................... 74
14. Special Function Registers................................................................................... 76
Rev. 1.0
3
C8051T630/1/2/3/4/5
15. Interrupts ................................................................................................................ 80
15.1. MCU Interrupt Sources and Vectors................................................................ 81
15.1.1. Interrupt Priorities.................................................................................... 81
15.1.2. Interrupt Latency ..................................................................................... 81
15.2. Interrupt Register Descriptions ........................................................................ 82
15.3. INT0 and INT1 External Interrupts................................................................... 87
16. EPROM Memory ..................................................................................................... 89
16.1. Programming and Reading the EPROM Memory ........................................... 89
16.1.1. EPROM Write Procedure ........................................................................ 89
16.1.2. EPROM Read Procedure........................................................................ 90
16.2. Security Options .............................................................................................. 90
16.3. Program Memory CRC .................................................................................... 91
16.3.1. Performing 32-bit CRCs on Full EPROM Content .................................. 91
16.3.2. Performing 16-bit CRCs on 256-Byte EPROM Blocks............................ 91
17. Power Management Modes................................................................................... 92
17.1. Idle Mode......................................................................................................... 92
17.2. Stop Mode ....................................................................................................... 93
17.3. Suspend Mode ................................................................................................ 93
18. Reset Sources ........................................................................................................ 95
18.1. Power-On Reset .............................................................................................. 96
18.2. Power-Fail Reset/VDD Monitor ....................................................................... 97
18.3. External Reset ................................................................................................. 98
18.4. Missing Clock Detector Reset ......................................................................... 98
18.5. Comparator0 Reset ......................................................................................... 99
18.6. PCA Watchdog Timer Reset ........................................................................... 99
18.7. EPROM Error Reset ........................................................................................ 99
18.8. Software Reset ................................................................................................ 99
19. Oscillators and Clock Selection ......................................................................... 101
19.1. System Clock Selection................................................................................. 101
19.2. Programmable Internal High-Frequency (H-F) Oscillator .............................. 103
19.2.1. Internal Oscillator Suspend Mode ......................................................... 103
19.3. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 105
19.3.1. Calibrating the Internal L-F Oscillator.................................................... 105
19.4. External Oscillator Drive Circuit..................................................................... 106
19.4.1. External RC Example............................................................................ 108
19.4.2. External Capacitor Example.................................................................. 108
20. Port Input/Output ................................................................................................. 109
20.1. Port I/O Modes of Operation.......................................................................... 110
20.1.1. Port Pins Configured for Analog I/O...................................................... 110
20.1.2. Port Pins Configured For Digital I/O...................................................... 110
20.1.3. Interfacing Port I/O to 5V Logic ............................................................. 111
20.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 112
20.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 112
20.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 112
20.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 113
4
Rev. 1.0
C8051T630/1/2/3/4/5
20.3. Priority Crossbar Decoder ............................................................................. 114
20.4. Port I/O Initialization ...................................................................................... 116
20.5. Port Match ..................................................................................................... 118
20.6. Special Function Registers for Accessing and Configuring Port I/O ............. 121
21. SMBus................................................................................................................... 127
21.1. Supporting Documents .................................................................................. 128
21.2. SMBus Configuration..................................................................................... 128
21.3. SMBus Operation .......................................................................................... 128
21.3.1. Transmitter Vs. Receiver....................................................................... 129
21.3.2. Arbitration.............................................................................................. 129
21.3.3. Clock Low Extension............................................................................. 129
21.3.4. SCL Low Timeout.................................................................................. 129
21.3.5. SCL High (SMBus Free) Timeout ......................................................... 130
21.4. Using the SMBus........................................................................................... 130
21.4.1. SMBus Configuration Register.............................................................. 130
21.4.2. SMB0CN Control Register .................................................................... 134
21.4.2.1. Software ACK Generation ............................................................ 134
21.4.2.2. Hardware ACK Generation ........................................................... 134
21.4.3. Hardware Slave Address Recognition .................................................. 136
21.4.4. Data Register ........................................................................................ 139
21.5. SMBus Transfer Modes................................................................................. 140
21.5.1. Write Sequence (Master) ...................................................................... 140
21.5.2. Read Sequence (Master) ...................................................................... 141
21.5.3. Write Sequence (Slave) ........................................................................ 142
21.5.4. Read Sequence (Slave) ........................................................................ 143
21.6. SMBus Status Decoding................................................................................ 143
22. UART0 ................................................................................................................... 148
22.1. Enhanced Baud Rate Generation.................................................................. 149
22.2. Operational Modes ........................................................................................ 150
22.2.1. 8-Bit UART ............................................................................................ 150
22.2.2. 9-Bit UART ............................................................................................ 151
22.3. Multiprocessor Communications ................................................................... 152
23. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 156
23.1. Signal Descriptions........................................................................................ 157
23.1.1. Master Out, Slave In (MOSI)................................................................. 157
23.1.2. Master In, Slave Out (MISO)................................................................. 157
23.1.3. Serial Clock (SCK) ................................................................................ 157
23.1.4. Slave Select (NSS) ............................................................................... 157
23.2. SPI0 Master Mode Operation ........................................................................ 158
23.3. SPI0 Slave Mode Operation .......................................................................... 159
23.4. SPI0 Interrupt Sources .................................................................................. 160
23.5. Serial Clock Phase and Polarity .................................................................... 160
23.6. SPI Special Function Registers ..................................................................... 162
24. Timers ................................................................................................................... 169
24.1. Timer 0 and Timer 1 ...................................................................................... 171
Rev. 1.0
5
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
