ST72324BJ4TD/XXXXS datasheet, PDF - EEWORLD Datasheet

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ST72324BJ4TD/XXXXS: Description8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP44, 10 X 10 MM, ROHS COMPLIANT, LQFP-44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，198 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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ST72324BJ4TD/XXXXS Overview

8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP44, 10 X 10 MM, ROHS COMPLIANT, LQFP-44

ST72324BJ4TD/XXXXS Parametric

Parameter Name	Attribute value
Objectid	1036736969
Parts packaging code	QFP
package instruction	10 X 10 MM, ROHS COMPLIANT, LQFP-44
Contacts	44
Reach Compliance Code	compliant
Has ADC	YES
Other features	ALSO OPERATES AT 3.8 V MINIMUM SUPPLY
Address bus width
bit size	8
maximum clock frequency	8 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	S-PQFP-G44
length	10 mm
Number of I/O lines	32
Number of terminals	44
On-chip program ROM width	8
Maximum operating temperature	115 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
RAM (bytes)	512
rom(word)	16384
ROM programmability	MROM
Maximum seat height	1.6 mm
speed	8 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
width	10 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST72324Bxx-Auto

8-bit MCU for automotive, 3.8 to 5.5V operating range with

8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI

Features

Memories

■

8 to 32 Kbyte dual voltage High Density Flash

(HDFlash) or ROM with readout protection

capability. In-application programming and In-

circuit programming for HDFlash devices

■

384 bytes to 1 Kbyte RAM

■

HDFlash endurance: 100 cycles, data retention

20 years

LQFP44

10 x 10

LQFP32

7x7

4 timers

■

Clock, reset and supply management

■

Enhanced low voltage supervisor (LVD) with

programmable reset thresholds and auxiliary

voltage detector (AVD) with interrupt capability

■

Clock sources: crystal/ceramic resonator

oscillators, internal RC oscillator and external

clock input

■

PLL for 2x frequency multiplication

■

4 power saving modes: Slow, Wait, Active Halt,

and Halt

Main clock controller with Real-time base,

Beep and Clock-out capabilities

■

Configurable watchdog timer

■

16-bit Timer A with 1 input capture, 1 output

compare, external clock input, PWM and pulse

generator modes

■

16-bit Timer B with 2 input captures, 2 output

compares, PWM and pulse generator modes

2 communication interfaces

■

SPI synchronous serial interface

■

SCI asynchronous serial interface

Interrupt management

■

1 analog peripheral (low current coupling)

■

Nested interrupt controller

■

10 interrupt vectors plus TRAP and RESET

■

9/6 external interrupt lines (on 4 vectors)

10-bit ADC with up to 12 input ports

Instruction set

■

Up to 32 I/O ports

■

32/24 multifunctional bidirectional I/O lines

■

22/17 alternate function lines

■

12/10 high sink outputs

8-bit data manipulation

■

63 basic instructions

■

17 main addressing modes

■

8 x 8 Unsigned Multiply Instruction

Development tools

■

In-circuit testing capability

Table 1.

Device

Device summary

Memory

RAM (stack)

384 (256) bytes

512 (256) bytes

1024 (256) bytes

384 (256) bytes

512 (256) bytes

1024 (256) bytes

3.8 to 5.5V

up to

-40 to 125°C

LQFP44

10x10

LQFP32

7x7

Voltage range

Temp. range

Package

ST72324BK2-Auto Flash/ROM 8 Kbytes

ST72324BK4-Auto Flash/ROM 16 Kbytes

ST72324BK6-Auto Flash/ROM 32 Kbytes

ST72324BJ2-Auto Flash/ROM 8 Kbytes

ST72324BJ4-Auto Flash/ROM 16 Kbytes

ST72324BJ6-Auto Flash/ROM 32 Kbytes

July 2010

Doc ID13466 Rev 4

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www.st.com

1

Contents

ST72324B-Auto

Contents

1

2

3

4

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1

4.2

4.3

4.4

4.5

4.6

4.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.1

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.7.1

Flash Control/Status Register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5

Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1

5.2

5.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Stack Pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1

6.2

6.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PLL (phase locked loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.1

6.3.2

External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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Contents

Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.4

6.5

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.1

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.5.1

6.5.2

6.5.3

6.5.4

LVD (low voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

AVD (auxiliary voltage detector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.6

SI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.6.1

System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 39

7

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.1

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.1

7.2.2

7.2.3

7.2.4

Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3

7.4

7.5

Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.5.1

7.5.2

CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 46

7.6

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.6.1

7.6.2

I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 49

8

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1

8.2

8.3

8.4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.4.1

8.4.2

Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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Contents

ST72324B-Auto

9.1

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.2.1

9.2.2

9.2.3

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.3

9.4

9.5

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.5.1

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1

Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.1

10.1.2

10.1.3

10.1.4

10.1.5

10.1.6

10.1.7

10.1.8

10.1.9

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

How to program the Watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 66

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Hardware Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 68

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.2

Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 69

10.2.1

10.2.2

10.2.3

10.2.4

10.2.5

10.2.6

10.2.7

Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Real-time clock (RTC) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

MCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3

16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3.1

10.3.2

10.3.3

10.3.4

10.3.5

10.3.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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10.3.7

Contents

16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.4

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.4.1

10.4.2

10.4.3

10.4.4

10.4.5

10.4.6

10.4.7

10.4.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

10.5

Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.5.1

10.5.2

10.5.3

10.5.4

10.5.5

10.5.6

10.5.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

10.6

10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

10.6.1

10.6.2

10.6.3

10.6.4

10.6.5

10.6.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

11

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

11.1

CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

11.1.1

11.1.2

11.1.3

11.1.4

11.1.5

11.1.6

11.1.7

Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

11.2

Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Doc ID13466 Rev 4

5/198

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