Multi-Purpose Flash + SRAM ComboMemory
SST32VF802 / SST32VF162 / SST32VF164
FEATURES:
• MPF + SRAM ComboMemory
– SST32VF802: 512K x16 Flash + 128K x16 SRAM
– SST32VF162: 1M x16 Flash + 128K x16 SRAM
– SST32VF164: 1M x16 Flash + 256K x16 SRAM
• Single 2.7-3.6V Read and Write Operations
• Concurrent Operation
– Read from or write to SRAM while Erase/
Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 15 mA (typical)
for Flash or SRAM Read
– Standby Current: 20µA (typical)
• Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
Advance Information
• Fast Read Access Times:
– Flash: 70 ns
– SRAM: 70 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time:
SST32VF802: 8 seconds (typical)
SST32VF162/164: 15 seconds (typical)
• Flash Automatic Erase and Program Timing
– Internal V
PP
Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
– 48-Ball TBGA (10mm x 12mm)
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PRODUCT DESCRIPTION
The SST32VF802/162/164 ComboMemory devices in-
tegrate a 512K x16 or 1M x16 CMOS flash memory bank
with a 128K x16 or 256K x16 CMOS SRAM memory
bank in a Multi-Chip Package (MCP), manufactured with
SST’s proprietary, high performance SuperFlash
technology.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time
of 14 µsec. The entire flash memory bank can be erased
and programmed word-by-word in typically 8 seconds for
the SST32VF802 and 15 seconds for the SST32VF162/
164, when using interface features such as Toggle Bit or
Data# Polling to indicate the completion of Program
operation. To protect against inadvertent flash write, the
SST32VF802/162/164 devices contain on-chip hard-
ware and software data protection schemes.The
SST32VF802/162/164 devices offer a guaranteed en-
durance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST32VF802/162/164 devices consist of two inde-
pendent memory banks with respective bank enable
signals. The Flash and SRAM memory banks are super-
imposed in the same memory address space. Both
memory banks share common address lines, data lines,
WE# and OE#. The memory bank selection is done by
memory bank enable signals. The SRAM bank enable
signal, BES# selects the SRAM bank. The flash memory
© 2000 Silicon Storage Technology, Inc.
362-09 2/00
bank enable signal, BEF# selects the flash memory
bank. The WE# signal has to be used with Software Data
Protection (SDP) command sequence when controlling
the Erase and Program operations in the flash memory
bank. The SDP command sequence protects the data
stored in the flash memory bank from accidental
alteration.
The SST32VF802/162/164 provide the added function-
ality of being able to simultaneously read from or write to
the SRAM bank while erasing or programming in the
flash memory bank. The SRAM memory bank can be
read or written while the flash memory bank performs
Sector-Erase, Bank-Erase, or Word-Program concur-
rently. All flash memory Erase and Program operations
will automatically latch the input address and data sig-
nals and complete the operation in background without
further input stimulus requirement. Once the internally
controlled erase or program cycle in the flash bank has
commenced, the SRAM bank can be accessed for read
or write.
The SST32VF802/162/164 devices are suited for appli-
cations that use both flash memory and SRAM memory
to store code or data. For systems requiring low power
and small form factor, the SST32VF802/162/164 de-
vices significantly improve performance and reliability,
while lowering power consumption, when compared
with multiple chip solutions. The SST32VF802/162/164
inherently use less energy during erase and program
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF and ComboMemory are trademarks of
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Silicon Storage Technology, Inc. These specifications are subject to change without notice.
Multi-Purpose Flash + SRAM ComboMemory
SST32VF802 / SST32VF162 / SST32VF164
Advance Information
than alternative flash technologies. The total energy
consumed is a function of the applied voltage, current,
and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to
program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less
than alternative flash technologies.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the sys-
tem software or hardware does not have to be modified
or de-rated as is necessary with alternative flash tech-
nologies, whose Erase and Program times increase with
accumulated Erase/Program cycles.
Device Operation
The ComboMemory uses BES# and BEF# to control
operation of either the SRAM or the flash memory bank.
When BES# is low, the SRAM Bank is activated for Read
and Write operation. When BEF# is low the flash bank is
activated for Read, Program or Erase operation. BES#
and BEF# cannot be at low level at the same time. If
BES# and BEF# are both asserted to low level bus
contention will result and the device may suffer perma-
nent damage. All address, data, and control lines are
shared by SRAM Bank and flash bank which minimizes
power consumption and loading. The device goes into
standby when both bank enables are high.
SRAM Operation
With BES# low and BEF# high, the SST32VF802/162
operate as 128K x16 CMOS SRAM, and the
SST32VF164 operates as 256K x16 CMOS SRAM, with
fully static operation requiring no external clocks or
timing strobes. The SST32VF802/162 SRAM is mapped
into the first 128 KWord address space of the device, and
the SST32VF164 SRAM is mapped into the first 256
KWord address space. When BES# and BEF# are high,
both memory banks are deselected and the device
enters standby mode. Read and Write cycle times are
equal. The control signals UBS# and LBS# provide
access to the upper data byte and lower data byte. See
Table 3 for SRAM read and write data byte control modes
of operation.
SRAM Read
The SRAM Read operation of the SST32VF802/162/164
is controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when OE#
is high. Refer to the Read cycle timing diagram, Figure 2,
for further details.
© 2000 Silicon Storage Technology, Inc.
SRAM Write
The SRAM Write operation of the SST32VF802/162/164
is controlled by WE# and BES#, both have to be low and
OE# must be high for the system to write to the SRAM.
During the Word-Write operation, the addresses and
data are referenced to the rising edge of either BES# or
WE#, whichever occurs first. The write time is measured
from the last falling edge to the first rising edge of BES#
and WE#. Refer to the Write cycle timing diagram, Figure
3, for further details.
Flash Operation
With BEF# active, the SST32VF162/164 operate as 1M
x16 flash memory and the SST32VF802 operates as
512K x16 flash memory. The flash memory bank is read
using the common address lines, data lines, WE# and
OE#. Erase and Program operations are initiated with
the JEDEC standard SDP command sequences. Ad-
dress and data are latched during the SDP commands
and during the internally timed Erase and Program
operations.
Flash Read
The Read operation of the SST32VF802/162/164 de-
vices is controlled by BEF# and OE#. Both have to be
low, with WE# high, for the system to obtain data from the
outputs. BEF# is used for flash memory bank selection.
When BEF# and BES# are high, both banks are dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when OE#
is high. Refer to Figure 4 for further details.
Flash Erase/Program Operation
SDP commands are used to initiate the flash memory
bank Program and Erase operations of the
SST32VF802/162/164. SDP commands are loaded to
the flash memory bank using standard microprocessor
write sequences. A command is loaded by asserting
WE# low while keeping BEF# low and OE# high. The
address is latched on the falling edge of WE# or BEF#,
whichever occurs last. The data is latched on the rising
edge of WE# or BEF#, whichever occurs first.
Flash Word-Program Operation
The flash memory bank of the SST32VF802/162/164
devices is programmed on a word-by-word basis. The
Program operation consists of three steps. The first step
is the three-byte-load sequence for Software Data Pro-
tection. The second step is to load word address and
word data. During the Word-Program operation, the
addresses are latched on the falling edge of either BEF#
or WE#, whichever occurs last. The data is latched on the
rising edge of either BEF# or WE#, whichever occurs
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362-09 2/00
Multi-Purpose Flash + SRAM ComboMemory
SST32VF802 / SST32VF162 / SST32VF164
Advance Information
first. The third step is the internal Program operation
which is initiated after the rising edge of the fourth WE#
or BEF#, whichever occurs first. The Program operation,
once initiated, will be completed, within 20 µs. See
Figures 5 and 6 for WE# and BEF# controlled Program
operation timing diagrams and Figure 16 for flowcharts.
During the Program operation, the only valid flash Read
operations are Data# Polling and Toggle Bit. During the
internal Program operation, the host is free to perform
additional tasks. Any SDP commands loaded during the
internal Program operation will be ignored.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the sys-
tem to erase the device on a sector-by-sector (or block-
by-block) basis. The SST32VF802/162/164 offer both
small Sector-Erase and Block-Erase mode. The sector
architecture is based on uniform sector size of 2 KWord.
The Block-Erase mode is based on uniform block size of
32 KWord. The Sector-Erase operation is initiated by
executing a six-byte command sequence with Sector-
Erase command (30H) and sector address (SA) in the
last bus cycle. The address lines A19-A11, for
SST32VF162/164, and A18-A11, for SST32VF802, are
used to determine the sector address. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The address lines
A19-A15, for SST32VF162/164, and A18-A15, for
SST32VF802, are used to determine the block address.
The sector or block address is latched on the falling edge
of the sixth WE# pulse, while the command (30H or 50H)
is latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE#
pulse. The End-of-Erase operation can be determined
using either Data# Polling or Toggle Bit methods. See
Figures 10 and 11 for timing waveforms. Any commands
issued during the Sector- or Block-Erase operation are
ignored.
Flash Chip-Erase Operation
The SST32VF802/162/164 provide a Chip-Erase opera-
tion, which allows the user to erase the entire memory
array to the “1” state. This is useful when the entire device
must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data#
Polling. See Table 4 for the command sequence, Figure
8 for timing diagram, and Figure 19 for the flowchart. Any
commands issued during the Chip-Erase operation are
ignored.
Write Operation Status Detection
The SST32VF802/162/164 provide two software means
to detect the completion of a write (Program or Erase)
cycle, in order to optimize the system write cycle time.
The software detection includes two status bits: Data#
Polling (DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write
detection mode is enabled after the rising edge of WE#,
which initiates the internal program or erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ
7
or DQ
6
. In order to
prevent spurious rejection, if an erroneous result occurs,
the software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the write
cycle, otherwise the rejection is valid.
Flash Data# Polling (DQ7)
When the SST32VF802/162/164 flash memory banks
are in the internal Program operation, any attempt to read
DQ7 will produce the complement of the true data. Once
the Program operation is completed, DQ7 will produce
true data. The flash memory bank is then ready for the
next operation. During internal Erase operation, any
attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ7 will produce a ‘1’.
The Data# Polling is valid after the rising edge of the
fourth WE# (or BEF#) pulse for Program operation. For
Sector- or Block-Erase, the Data# Polling is valid after
the rising edge of the sixth WE# (or BEF#) pulse. See
Figure 7 for Data# Polling timing diagram and Figure 17
for a flowchart.
Flash Toggle Bit (DQ6)
During the internal Program or Erase operation, any
consecutive attempts to read DQ6 will produce alternat-
ing 1’s and 0’s, i.e., toggling between 1 and 0. When the
internal Program or Erase operation is completed, the
toggling will stop. The flash memory bank is then ready
for the next operation. The Toggle Bit is valid after the
rising edge of the fourth WE# (or BEF#) pulse for
Program operation. For Sector- or Bank-Erase, the
Toggle Bit is valid after the rising edge of the sixth WE#
(or BEF#) pulse. See Figure 8 for Toggle Bit timing
diagram and Figure 17 for a flowchart.
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362-09 2/00
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© 2000 Silicon Storage Technology, Inc.
Multi-Purpose Flash + SRAM ComboMemory
SST32VF802 / SST32VF162 / SST32VF164
Advance Information
Flash Memory Data Protection
The SST32VF802/162/164 flash memory bank provides
both hardware and software features to protect nonvola-
tile data from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less
than 5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Flash Software Data Protection (SDP)
The SST32VF802/162/164 provide the JEDEC ap-
proved software data protection scheme for all flash
memory bank data alteration operations, i.e., Program
and Erase. Any Program operation requires the inclusion
of a series of three-byte sequence. The three byte-load
sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write op-
erations, e.g., during the system power-up or power-
down. Any Erase operation requires the inclusion of six-
byte load sequence. The SST32VF802/162/164 devices
are shipped with the software data protection perma-
nently enabled. See Table 4 for the specific software
command codes. During SDP command sequence, in-
valid SDP commands will abort the device to the read
mode, within Read Cycle Time (TRC).
Concurrent Read and Write Operations
The SST32VF802/162/164 provide the unique benefit of
being able to read from or write to SRAM, while simulta-
neously erasing or programming the Flash. This allows
data alteration code to be executed from SRAM, while
altering the data in Flash. The following table lists all valid
states.
C
ONCURRENT
R
EAD
/W
RITE
S
TATE
T
ABLE
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
Product Identification
The product identification mode identifies the devices as
the SST32VFxxx and manufacturer as SST.
This mode
may be accessed by software operations only. The
hardware device ID Read operation, which is typi-
cally used by programmers, cannot be used on this
device because of the shared lines between flash
and SRAM in the multi-chip package. Therefore,
application of high voltage to pin A9 may damage
this device.
Users may use the software product iden-
tification operation to identify the part (i.e., using the
device code) when using multiple manufacturers in the
same socket. For details, see Tables 3 and 4 for software
operation, Figure 12 for the software ID entry and read
timing diagram and Figure 18 for the ID entry command
sequence flowchart.
T
ABLE
1: P
RODUCT
I
DENTIFICATION
T
ABLE
Address
Manufacturer’s Code
Device Code for SST32VF802
Device Code for SST32VF162/164
0000H
0001H
0001H
Data
00BF H
2781 H
2782 H
362 PGM T1.5
Product Identification Mode Exit/Reset
In order to return to the standard read mode, the Soft-
ware Product Identification mode must be exited. Exiting
is accomplished by issuing the Exit ID command se-
quence, which returns the device to the Read operation.
Please note that the software-reset command is ignored
during an internal Program or Erase operation. See
Table 4 for software command codes, Figure 13 for
timing waveform and Figure 18 for a flowchart.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic
capacitor to be placed as close as possible between V
DD
and V
SS
, e.g., less than 1 cm away from the V
DD
pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from V
DD
to V
SS
should be placed within 1 cm
of the V
DD
pin.
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these
commands will also be ignored while an Erase or Pro-
gram operation is in progress.
© 2000 Silicon Storage Technology, Inc.
4
362-09 2/00
Multi-Purpose Flash + SRAM ComboMemory
SST32VF802 / SST32VF162 / SST32VF164
Advance Information
F
UNCTIONAL
B
LOCK
D
IAGRAM
Address Buffers
SRAM
Cell Array
1
2
AMS
(1)
-A0
UBS#
LBS#
BES#
BEF#
OE#
WE#
Control Logic
I/O Buffers
DQ15 - DQ8
DQ7 - DQ0
3
4
Address Buffers
& Latches
Flash
Cell Array
362 ILL B1.6
5
TOP VIEW (balls facing down)
TOP VIEW (balls facing down)
6
6
5
4
3
A11
A8
A5
DQ8
DQ3 DQ12
A12 LBS#
BES# VSS DQ1
A10 DQ5 DQ2
OE# DQ7 DQ4
A1
A0
DQ0
A2
A3
A6
A4
A7
A18
NC
NC
NC
6
A9
A14
A15
BES# VSS DQ1
A10 DQ5 DQ2
OE# DQ7 DQ4
A11
A8
A5
A1
A0
DQ0
DQ8
A2
A3
A6
A4
A7
A18
A19
NC
NC
A9
A14
A15
5
4
3
2
7
8
362 ILL F01.6
DQ3 DQ12
A12 LBS#
DQ6 DQ15
2
A13
A17 UBS# BEF# DQ10 VDDF
VSS
DQ6 DQ15
WE# VDDS A16
DQ9 DQ11 DQ13 DQ14
A13
A17 UBS# BEF# DQ10 VDDF
VSS
362 ILL F01a.0
1
1
WE# VDDS A16
DQ9 DQ11 DQ13 DQ14
9
10
11
12
13
14
15
16
A B C D E F G H
SST32VF802
A B C D E F G H
SST32VF162/SST32VF164
F
IGURE
1: P
IN
A
SSIGNMENTS
48-B
ALL
TBGA P
ACKAGE
T
ABLE
2: P
IN
D
ESCRIPTION
Symbol
Pin Name
(1)
-A
A
MS
Address Inputs
0
DQ
15
-DQ
0
Data Input/output
BES#
BEF#
OE#
WE#
V
DDF
V
DDS
Vss
UBS#
LBS#
NC
SRAM Memory Bank Enable
Flash Memory Bank Enable
Output Enable
Write Enable
Power Supply (Flash)
Power Supply (SRAM)
Ground
Upper Byte Control
Lower Byte Control
No Connection
Functions
To provide flash address, A
19
-A
0
for 16M, and A
18
-A
0
for 8M.
A
16
-A
0
for 2M and A
17
-A
0
for 4M to provide SRAM addresses.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
To activate the SRAM memory bank when BES# is low.
To activate the Flash memory bank when BEF# is low.
To gate the data output buffers.
To control the Write operations.
2.7-3.6V Power Supply to Flash only
2.7-3.6V Power Supply to SRAM only
To enable DQ
15
-DQ
8
To enable DQ
7
-DQ
0
Unconnected Pins
362 PGM T2.7
362-09 2/00
Note (1): A
MS
= Most significant address
© 2000 Silicon Storage Technology, Inc.
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