SIT9025AIB22H25DP25.000625E datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> SIT9025AIB22H25DP25.000625E

SIT9025AIB22H25DP25.000625E: DescriptionLVCMOS Output Clock Oscillator, 25.000625MHz Nom,; CategoryPassive components oscillator; File Size866KB，14 Pages; ManufacturerSiTime; Environmental Compliance

Download Datasheet Parametric View All

SIT9025AIB22H25DP25.000625E Overview

LVCMOS Output Clock Oscillator, 25.000625MHz Nom,

SIT9025AIB22H25DP25.000625E Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	145227952481
Reach Compliance Code	unknown
Other features	SPREAD DISABLE
maximum descent time	2.2 ns
Frequency Adjustment - Mechanical	NO
frequency stability	25%
JESD-609 code	e4
Installation features	SURFACE MOUNT
Number of terminals	4
Nominal operating frequency	25.000625 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVCMOS
Output load	15 pF
Maximum output low current	3 mA
Encapsulate equivalent code	DILCC4,.1,83
physical size	3.2mm x 2.5mm x 0.75mm
longest rise time	2.2 ns
Filter level	AEC-Q100
Maximum slew rate	9.5 mA
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)

SIT9025AIB22H25DP25.000625E Preview

SiT9025

Features



AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator

Applications



Spread spectrum for EMI reduction



Wide spread % option



Center spread: from ±0.125% to ±2%, ±0.125% step size



Down spread: -0.25% to -4% with -0.25% step size



Spread profile option: Triangular, Hershey-kiss, Random

Programmable rise/fall time for EMI reduction: 8 options,

0.25 to 40 ns

AEC-Q100 with extended temperature range (-55°C to 125°C)

Any frequency between 1 MHz and 150 MHz accurate to

6 decimal places

100% pin-to-pin drop-in replacement to quartz-based XO’s

Excellent total frequency stability as low as ±25 ppm



Contact SiTime

for ±20 ppm option

Low power consumption of 6.6 mA typical at 1.8 V

Pin1 modes: Standby, output enable, or spread disable

LVCMOS output

Industry-standard packages



QFN: 2.0 x 1.6 mm

, 2.5 x 2.0 mm

, 3.2 x 2.5 mm

RoHS and REACH compliant, Pb-free, Halogen-free and

Antimony-free

Rear/Surround view camera

Driver monitor

ADAS ECU/CPU

High speed serial link

Electrical Specifications

Table 1. Electrical Characteristics

All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated.

Typical values are at 25°C and 3.3 V supply voltage.

Parameters

Output Frequency Range

Frequency Stability

[1]

Symbol

F_stab

Min.

-25

-50

Typ.

–

1.8

2.5

2.8

3.0

3.3

–

7.9

6.6

5.3

5.0

2.6

0.6

Max.

150

+25

+50

+85

+105

+125

1.98

2.75

3.08

3.3

3.63

9.5

8.0

6.5

6.0

9.0

5.0

Unit

MHz

ppm

°C

µA

Condition

Frequency Range

Frequency Stability and Aging

Inclusive of initial tolerance at 25°C, 1st year aging at 25°C, and

variations over operating temperature, rated power supply voltage.

Spread = Off.

AEC-Q100 Grade 3

AEC-Q100 Grade 2

AEC-Q100 Grade 1

Extended cold AEC-Q100 Grade 1

Operating Temperature Range

Operating Temperature

Range

T_use

-40

-55

Supply Voltage

Vdd

1.62

2.25

2.52

2.7

2.97

2.25

Current Consumption

OE Disable Current

Standby Current

Idd

I_OD

I_std

–

Supply Voltage and Current Consumption

No load condition, f = 148.5 MHz, Vdd = 2.5 V to 3.3 V

No load condition, f = 148.5 MHz, Vdd = 1.8 V

f = 148.5 MHz, Vdd = 2.5 V to 3.3 V, OE = GND, Output in high-Z state

f = 148.5 MHz, Vdd = 1.8 V, OE = GND, Output in high-Z state

= GND, Vdd = 2.5 V to 3.3 V, Output is weakly pulled down

= GND, Vdd = 1.8 V, Output is weakly pulled down

Rev 1.01

September 9, 2020

www.sitime.com

SiT9025

AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator

Table 1. Electrical Characteristics

(continued)

Parameters

Duty Cycle

Rise/Fall Time

Output High Voltage

Symbol

Tr, Tf

VOH

Min.

–

90%

Typ.

–

1.2

–

Max.

2.0

–

Unit

Vdd

f = 1 to 137 MHz

f = 137.000001 to 150 MHz

20% - 80%, default derive strength

IOH = -4 mA (Vdd = 3.0 V or 3.3 V)

IOH = -3 mA (Vdd = 2.8 V and Vdd = 2.5 V)

IOH = -2 mA (Vdd = 1.8 V)

IOL = 4 mA (Vdd = 3.0 V or 3.3 V)

IOL = 3 mA (Vdd = 2.8 V and Vdd = 2.5 V)

IOL = 2 mA (Vdd = 1.8 V)

Pin 1, OE or

Pin1,

logic low

Pin1,

logic high

Pin1, OE / SD logic low

Pin1, OE / SD logic high

Measured from the time Vdd reaches its rated minimum value

f = 148.5 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles

Measured from the time ST pin crosses 50% threshold

Measured from the time SD pin crosses 50% threshold

f = 148.5 MHz, Vdd = 2.5 to 3.3 V, Spread = ON (or OFF)

f = 148.5 MHz, Vdd = 1.8 V, Spread = ON (or OFF)

Condition

LVCMOS Output Characteristics

Output Low Voltage

VOL

–

10%

Vdd

Input Characteristics

Input High Voltage

Input Low Voltage

Input Leakage Current

VIH

VIL

70%

–

Startup Time

Enable/Disable Time

Resume Time

Spread Enable Time

Spread Disable Time

Cycle-to-cycle jitter

Note:

T_start

T_oe

T_resume

T_sde

T_sdde

T_ccj

–

Contact SiTime

for ±20 ppm option.

–

-2.3

2.8

-24.6

3.2

–

10.5

10.8

–

30%

–

215

–

Vdd

µA

µs

Jitter

Startup and Resume Timing

Table 2. Spread Spectrum %

[3]

Ordering Code

Center Spread

(%)

±0.125

±0.250

±0.390

±0.515

±0.640

±0.765

±0.905

±1.030

±1.155

±1.280

±1.420

±1.545

±1.670

±1.795

±1.935

±2.060

Down Spread

(%)

-0.25

-0.50

-0.78

-1.04

-1.29

-1.55

-1.84

-2.10

-2.36

-2.62

-2.91

-3.18

-3.45

-3.71

-4.01

-4.28

Table 3. Spread Profile

[2,3]

Spread Profile

Triangular

Hershey-kiss

Random

Notes:

2. In both Triangular and Hershey-kiss profiles, modulation rate is

employed with a frequency of ~31.25 kHz. In random profile,

modulation rate is ~ 8.6 kHz.

3. The random profile supports up to ±1.030% center spread

or -2.10% down spread (ordering codes A through H).

Rev 1.01

Page 2 of 3

www.sitime.com

SiT9025

AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator

Table 4. Pin Description

Symbol

OE /

NC/ SD

Output

Enable

Standby

Functionality

[4]

: specified frequency output

L: output is high impedance. Only output driver is disabled.

H : specified frequency output

L: output is low (week pull down). Device goes to sleep mode.

Supply current reduced to I_std.

[4]

Top View

OE /

NC / SD

VDD

No Connect

Spread

Disable

Notes:

GND

OUT

VDD

Power

Output

Power

Pin1 has no function (Any voltage between 0 and Vdd or Open)

H: Spread = ON

L: Spread = OFF

Electrical ground

Oscillator output

Power supply voltage

[5]

GND

OUT

Figure 1. Pin Assignments

4. In OE or

mode, a pull-up resistor of 10

kΩ

or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.

5. A capacitor of value 0.1 µF or higher between Vdd and GND is required.

Table 5. Absolute Maximum Limits

Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the

IC is only guaranteed within the operational specifications, not at absolute maximum ratings.

Parameter

Storage Temperature

Vdd

Electrostatic Discharge

Soldering Temperature (follow standard Pb free soldering guidelines)

Junction Temperature

[6]

Note:

6. Exceeding this temperature for extended period of time may damage the device.

Min.

-65

-0.5

–

Max.

150

2000

260

150

Unit

°C

Table 6. Maximum Operating Junction Temperature

[7]

Max Operating Temperature (ambient)

85°C

105°C

125°C

Note:

Maximum Operating Junction Temperature

95°C

115°C

135°C

7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.

Table 7. Environmental Compliance

Parameter

Mechanical Shock

Mechanical Vibration

Temperature Cycle

Solderability

Moisture Sensitivity Level

Condition/Test Method

MIL-STD-883F, Method 2002

MIL-STD-883F, Method 2007

JESD22, Method A104

MIL-STD-883F, Method 2003

MSL1 @ 260°C

Rev 1.01

Page 3 of 4

www.sitime.com

SiT9025

AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator

Timing Diagrams

90% Vdd

Pin 4 Voltage

Vdd

50% Vdd

T_resume

T_start

No Glitch

[8]

during start up

ST Voltage

CLK Output

T_resume: Time to resume from ST

T_start: Time to start from power-off

Figure 2. Startup Timing

Figure 3. Standby Resume Timing (ST Mode Only)

50% Vdd

OE Voltage

CLK Output

Vdd

T_oe

Vdd

OE Voltage

50% Vdd

T_oe

CLK Output

T_oe: Time to put the output in High Z mode

T_oe: Time to re-enable the clock output

Figure 4. OE Enable Timing (OE Mode Only)

Figure 5. OE Disable Timing (OE Mode Only)

Vdd

50% Vdd

SD Voltage

T_sde

SD Voltage

Vdd

50% Vdd

T_sdde

Frequency

Deviation (%)

Modulation period = 32 µs (31.25 kHz)

Time (s)

Frequency

Deviation (%)

Time (s)

Figure 6. SD Enable Timing (SD Mode Only)

Note:

8. SiT9025 has “no runt” pulses and “no glitch” output during startup or resume.

Figure 7. SD Diable Timing (SD Mode Only)

Rev 1.01

Page 4 of 5

www.sitime.com

SiT9025

AEC-Q100, 1 to 150 MHz EMI Reduction Oscillator

Performance Plots

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

5.4

8.0

Current Consumption (mA)

5.2

5.0

4.8

4.6

4.4

OE Disable Current (mA)

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

100

120

140

100

120

140

Frequency (MHz)

Figure 8. OE Disable Current vs Frequency

Figure 9. Current Consumption vs Frequency

DUT1

DUT8

DUT15

DUT2

DUT9

DUT16

DUT3

FUT10

DUT17

DUT4

DUT11

DUT18

DUT5

DUT12

DUT19

DUT6

DUT13

DUT20

DUT7

DUT14

1.8 V

2.5 V

2.8 V

3.0 V

3.3 V

2.5

2.0

1.5

1.0

0.5

0.0

Frequency stability (ppm)

100

120

140

-5

-10

-15

-20

-40

-20

100

120

Standby Current (µA)

Frequency (MHz)

Temperature (°C)

Figure 10. Standby Current vs Frequency

1.8V

2.5V

2.8V

3.0V

3.3V

Figure 11. Frequency vs Temperature

Peak Cycle -to - Cycle Jitter (ps)

100

120

140

Frequency (MHz)

Figure 12. Cycle-to-cycle Jitter vs Frequency

(Spread profile: Triangular, Spread type: center,

Spread percentage: ±2.060%)

Rev 1.01

Page 5 of 6

www.sitime.com

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

Recommended Resources

SL517 integrated circuit appearance and internal circuit

One of the light control switch circuits controlled by flashlight

Sample signal hold circuit

New three-phase phase-shifted trigger circuit schematic diagram

Tianjin ZT-2 hearing aid circuit

135 classic design examples of Verilog: ...; 至芯科技FPGA大牛 FPGA/CPLD

[Perf-V Evaluation] On-chip Temperature Collection: The routines provided with the development board provide an example of on-chip temperature acquisition, through which we can learn about A/D acquisition. In addition, since the driving display content...; jinglixixi FPGA/CPLD

100 Practical Tips for FPGA Design Experts (English Original).zip: 100 Practical Tips for FPGA Design Experts (English Original).zip...; zxopenljx EE_FPGA Learning Park

Huawei_Analog Circuit Design Volume 1: ...; 至芯科技FPGA大牛 FPGA/CPLD

Recruiting ADC/DAC application engineers, working location: Hangzhou: Hangzhou Songyangheng Technology Co., Ltd. - Recruitment Information:Position Information: ADC/DAC Application Engineer1. Cooperate with sales staff to expand domestic potential customers, and be resp...; 九里香 Recruitment

EEWORLD University Hall----New Raspberry Pi 4: Can it replace your PC?: The new Raspberry Pi 4: Can it replace your PC ? : https://training.eeworld.com.cn/course/5324The new Raspberry Pi 4: Can it replace your PC?...; 抛砖引玉 DIY/Open Source Hardware

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components