V826616J24SAIY-D3 datasheet, PDF

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V826616J24SAIY-D3: DescriptionDDR DRAM Module, 16MX64, 0.65ns, CMOS, PDMA184; Categorystorage storage; File Size309KB，15 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V826616J24SAIY-D3 Overview

DDR DRAM Module, 16MX64, 0.65ns, CMOS, PDMA184

V826616J24SAIY-D3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	1125506286
package instruction	DIMM, DIMM184
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	0.65 ns
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PDMA-N184
JESD-609 code	e4
memory density	1073741824 bit
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of terminals	184
word count	16777216 words
character code	16000000
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX64
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.6 V
Certification status	Not Qualified
refresh cycle	8192
Maximum slew rate	1.6 mA
Nominal supply voltage (Vsup)	2.6 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Gold (Au)
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

V826616J24SAIY-D3 Preview

V826616J24SA

16M x 64 HIGH PERFORMANCE

UNBUFFERED DDR SDRAM MODULE

Features

■

184 Pin Unbuffered 16,777,216 x 64 bit

Organization DDR SDRAM Modules

■

Utilizes High Performance 16M x 16 DDR

SDRAM in TSOPII-66 Packages

■

Single +2.5V (± 0.2V) Power Supply

■

Single +2.6V (± 0.1V) Power Supply for DDR400

■

Programmable CAS Latency, Burst Length, and

Wrap Sequence (Sequential & Interleave)

■

Auto Refresh (CBR) and Self Refresh

■

All Inputs, Outputs are SSTL-2 Compatible

■

8192 Refresh Cycles every 64 ms

■

Serial Presence Detect (SPD)

■

DDR SDRAM Performance

Module Speed

Description

The V826616J24SA memory module is orga-

nized 16,777,216 x 64 bits in a 184 pin memory

module. The 16M x 64 memory module uses 4 Pro-

MOS 16M x 16 DDR SDRAM. The x64 modules are

ideal for use in high performance computer systems

where increased memory density and fast access

times are required.

Clock Frequency

200

166

143

Module Speed

(PC400C (PC400B (PC400A (PC333) (PC26

(max.)

Clock Frequency

)

(max.)

)

200

)

6A)

(PC400A)

200

(PC400B)

166

(PC333)

143

(PC266A)

133

(PC266B)

Units

MHz

CLK

Clock Cycle Time 7.5

7.5

Clock Cycle Time CAS Latency = 2

CAS Latency = 2

Clock Cycle Time CAS Latency = 2.5

Clock Cycle Time CAS Latency = 3

RCD

tRCD parameter

tRP parameter

7.5

V826616J24SA Rev. 1.6 July 2004

ProMOS TECHNOLOGIES

Part Number Information

V826616J24SA

ProMOS

TYPE

8 : DDR

9 : DDR2

6 6

1 6

DATA

DEPTH

16 : 16Mb

32 : 32 Mb

64 : 64 Mb

65 : 128 Mb

66 : 256 Mb

PCB TYPE

G : GOLD_LEAD PLATING

REFRESH

RATE

0: 4K

1: 2K

2: 8K

3: 1K

BANKS

2 : 2 Banks

4 : 4 Banks

8 : 8 Banks

COMPONENT

REV LEVEL

W : GOLD_LEAD FREE

Y : GOLD_GREEN

L : LOW PROFILE_LEAD PLATING

X : LOW PROFILE_LEAD FREE

Z : LOW PROFILE_GREEN

VOLTAGE

2 : 2.5V

1: 1.8V

DATA WIDTH

& COMP DENSITY

X64 using 128M

X64 using 256M

X64 using 512M

X64 using 1G

X64 using 2G

X72 using 128M

X72 using 256M

X72 using 512M

X72 using 1G

X72 using 2G

MODULE TYPE

& COMP WIDTH

COMPONENT PKG

LEAD

LEAD GREEN PACKAGE

DESCRIPTION

TSOP

FBGA

BGA

Die-stacked TSOP

Die-stacked FBGA

SPEED

PLATING FREE

BASED ON

184PIN / 240PIN DIMM

UNBUFFERED

184PIN / 240PIN DIMM

REGISTERED

200PIN

SO-DIMM

172PIN

Micro-DIMM

X4 X16 X8

I/O INTERFACE

S: SSTL_2

Q: SSTL _18

B0 : PC2100B (133MHz @CL2.5-3-3)

B1 : PC2100A (133MHz @CL2-2-2)

C0 : PC2700 (166MHz @CL2.5-3-3)

D0 : PC3200 (200MHz @CL2.5-3-3)

D3 : PC3200 (200MHz @CL3-3-3)

V826616J24SA Rev. 1.6 July 2004

ProMOS TECHNOLOGIES

V826616J24SA

Block Diagram

DQS1

DM1/DQS10

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS5

DM5/DQS14

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS0

DM0/DQS9

DQS4

DM4/DQS13

DQS3

DM3/DQS12

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS2

DM2/DQS11

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQS7

DM7/DQS16

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS6

DM6/DQS15

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

Serial PD

SCL

SPD

DDQ

REF

DDID

SPD

D0 - D3

Strap: see Note 4

SA0

SA1

SA2

SDA

* Clock Wiring

Clock

SDRAMs

Input

*CK0/CK0

*CK1/CK1

*CK2/CK2

2 SDRAMs

* Wire per Clock Loading

Table/Wiring Diagrams

BA0 - BA1

A0 - A13

RAS

CAS

CKE0

BA0-BA1: SDRAMs D0 - D3

A0-A13: SDRAMs D0 - D3

RAS: SDRAMs D0 - D3

CAS: SDRAMs D0 - D3

CKE: SDRAMs D0 - D3

WE: SDRAMs D0 - D3

Notes:

1. DQ-to-I/O wiring is shown as recommended but may

be changed.

2. DQ/DQS/DM/CKE/S relationships must be main-

tained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms ± 5%.

4. V

DDID

strap connections

(for memory device V

, V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

DDQ

5. BA, Ax, RAS, CAS, WE resistors: 7.5 Ohms ± 5%

V826616J24SA Rev. 1.6 July 2004

ProMOS TECHNOLOGIES

Pin Configurations (Front Side/Back Side)

Front

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

VSS

DQ8

DQ9

DQS1

VDDQ

CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

Front

DQ24

VSS

DQ25

DQS3

VDD

DQ26

DQ27

Vss

CB0*

CB1*

VDD

DQS8*

CB2*

VSS

CB3*

BA1

Key Key

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

Front

VDDQ

DQ41

CAS

VSS

DQS5

DQ42

DQ43

VDD

DQ48

DQ49

VSS

CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Back

VSS

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

A13*

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

CKE1

VDDQ

BA2*

DQ20

A12

VSS

DQ21

A11

DM2

VDD

DQ22

DQ23

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

Back

VSS

DQ28

DQ29

VDDQ

DM3

DQ30

VSS

DQ31

CB4*

CB5*

VDDQ

CK0

VSS

DM8*

A10

CB6*

VDDQ

CB7*

Key key

VSS

DQ36

DQ37

VDD

DM4

DQ38

DQ39

VSS

DQ44

V826616J24SA

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

RAS

DQ45

VDDQ

CS0

CS1

DM5

VSS

DQ46

DQ47

VDDQ

DQ52

DQ53

VDD

DM6

DQ54

DQ55

VDDQ

DQ60

DQ61

VSS

DM7

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

Notes:

These pins are not used in this module.

Pin Names

CK0~ CK2, CK0~ CK2

CS0, CS1

CKE0, CKE1

RAS, CAS, WE

A0 ~ A12

BA0, BA1

DQ0~DQ63

DQS0~DQS7

DM0~DM7

VDD

Pin Description

Differential Clock Inputs

Chip Select Input

Clock Enable Input

Commend Sets Inputs

Address

Bank Address

Data Inputs/Outputs

Data Strobe Inputs/Outputs

Data-in Mask

Power Supply

VDDQ

VSS

VREF

VDDSPD

SA0~SA2

SCL

SDA

VDDID

Pin Description

DQs Power Supply

Ground

Reference Power Supply

Power Supply for SPD

PROM Address Inputs

PROM Clock

PROM Data I/O

VDD Identification Flag

Do not Use

No Connection

V826616J24SA Rev. 1.6 July 2004

ProMOS TECHNOLOGIES

Serial Presence Detect Information

Bin Sort:

D0 (PC3200 @ CL2.5-3-3)

D3 (PC3200 @ CL3-3-3 )

C0 (PC2700 @ CL2.5-3-3)

B1 (PC2100A @ CL2-2-2)

B0 (PC2100B @ CL2.5-3-3)

V826616J24SA

Byte

Function Supported

Function described

Defines # of Bytes written into serial memory at

module manufacturer

Total # of Bytes of SPD memory device

Fundamental memory type

# of row address on this assembly

# of column address on this assembly

# of module Rows on this assembly

Data width of this assembly

.........Data width of this assembly

VDDQ and interface standard of this assembly

DDR SDRAM cycle time at highest CAS Latency

5ns

Hex value

80h

128bytes

256bytes

SDRAM DDR

1 Bank

64 bits

SSTL 2.5V

6ns

7ns

7.5ns

50h

65h

08h

07h

0Dh

09h

01h

40h

00h

04h

60h

70h

75h

DDR SDRAM Access time from clock at highest ±0.65ns ±0.65ns±0.70ns ±0.75ns ±0.75ns 65h

DIMM configuration type(Non-parity, Parity, ECC)

Refresh rate & type

Primary DDR SDRAM width

Error checking DDR SDRAM data width

Minimum clock delay for back-to-back random

column

address

DDR SDRAM device attributes : Burst lengths

supported

DDR SDRAM device attributes : # of banks on

each DDR SDRAM

DDR SDRAM device attributes : CAS Latency

supported

DDR SDRAM device attributes : CS Latency

DDR SDRAM device attributes : WE Latency

DDR SDRAM module attributes

Non-parity, ECC

7.8us & Self refresh

x16

N/A

CCD

=1CLK

00h

82h

10h

00h

01h

2,4,8

0Eh

4 banks

04h

2, 2.5, 3

0Ch

1Ch

01h

02h

20h

0CLK

1CLK

Differential clock /

non Registered

+/-0.2V voltage tolerance

5.0ns

6.0ns

7.5ns

10ns

50h

60h

70h

DDR SDRAM device attributes : General

DDR SDRAM cycle time at second highest CL

00h

75h

70h

75h

A0h

75h

DDR SDRAM Access time from clock at second ±0.65ns ±0.70ns ±0.70ns ±0.75ns ±0.75ns 65h

highest CL

V826616J24SA Rev. 1.6 July 2004

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