CY7C1460SV25
CY7C1462SV25
36-Mbit (1M × 36/2M × 18)
Pipelined SRAM with NoBL™ Architecture
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture
Features
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Functional Description
The
CY7C1460SV25/CY7C1462SV25
are
2.5 V,
1M × 36/2M × 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back to back Read/Write
operations
with
no
wait
states.
The
CY7C1460SV25/CY7C1462SV25 are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent Write/Read transitions.
CY7C1460SV25/CY7C1462SV25 are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BW
a
–BW
d
for CY7C1460SV25 and BW
a
–BW
b
for
CY7C1462SV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
Pin compatible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
❐
Available speed grades are 250 and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
2.5-V core power supply
2.5-V I/O power supply
Fast clock-to-output times
❐
2.6 ns (for 250-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1460SV25 available in JEDEC-standard Pb-free 100-pin
TQFP package and non Pb-free 165-ball FBGA package.
CY7C1462SV25 available in Pb-free 100-pin TQFP package
IEEE 1149.1 JTAG-Compatible Boundary Scan
Burst capability – linear or interleaved burst order
“ZZ” Sleep Mode option and Stop Clock option
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Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
250 MHz
2.6
435
120
167 MHz
3.4
335
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-43804 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 7, 2016
CY7C1460SV25
CY7C1462SV25
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Burst Read Accesses .................................................. 7
Single Write Accesses ................................................. 7
Burst Write Accesses .................................................. 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Partial Write Cycle Description ..................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ............................... 15
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Identification Codes ....................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
DC Electrical Characteristics ..................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 20
Switching Characteristics .............................................. 21
Switching Waveforms .................................................... 22
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagrams .......................................................... 26
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC®Solutions ....................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-43804 Rev. *J
Page 3 of 31
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