SL23EP08
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
•
•
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10 to 220 MHz operating frequency range
Low output clock skew: 45ps-typ
Low output clock jitter:
25 ps-typ cycle-to-cycle jitter
15 ps-typ period jitter
Low part-to-part output skew: 90 ps-typ
Wide 2.5 V to 3.3 V power supply range
Low power dissipation:
20 mA-max at 66 MHz and VDD=3.3 V
18 mA-max at 66 MHz and VDD=2.5V
One input drives 8 outputs
Multiple configurations and drive options
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Datacom and Telecom
High-SpeedDigital Embeded Systems
Description
The SL23EP08 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9) clock
outputs from one (1) reference input clock, for high speed
clock distribution applications.
The product has an on-chip PLL and a feedback pin (FBK)
which can be used to obtain feedback from any one of the
output clocks. The SL23EP08 has two (2) clock driver banks
each with four (4) clock outputs. These outputs are controlled
by two (2) select input pins S1 and S2. When only four (4)
outputs are needed, four (4) bank-B output clock buffers can
be tri-stated to reduce power dissipation and jitter. The select
inputs can also be used to tri-state both banks A and B or
drive them directly from the input bypassing the PLL and
making the product behave like a Non-Zero Delay Buffer
(NZDB). The product also offers various 1X, 2X and 4X
frequency options at the output clocks. Refer to the “Product
Configuration Table” for the details.
The high-drive version operates up to 220MHz and 200MHz at
3.3V and 2.5V power supplies respectively.
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Applications
Benefits
•
•
•
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Up to eight (8) distribution of input clock
Standard and High-Dirive levels to control impedance
level, frequency range and EMI
Low power dissipation, jitter and skew
Low cost
Block Diagram
/2
(Divider for -3 and -4 only)
Low Power and
Low Jitter
CLKIN
/2
(Divider for -5H only)
PLL
MUX
FBK
CLKA1
CLKA2
CLKA3
S2
Input Selection
Decoding Logic
S1
/2
(Divider for -2 and -3 only)
CLKA4
CLKB1
CLKB2
CLKB3
2
2
CLKB4
VDD
GND
Rev 1.0, May 18, 2006
Page 1 of 15
2400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL23EP08
Pin Configuration
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
16-Pin SOIC and TSSOP
Pin Description
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
S1
CLKB3
CLKB4
GND
VDD
CLKA3
CLKA4
FBK
Pin Type
Input
Output
Output
Power
Power
Output
Output
Input
Input
Output
Output
Power
Power
Output
Output
Output
Pin Description
Reference Frequency Clock Input. 5V tolerant input. Weak pull-down (250kΩ).
Buffered Clock Output, Bank A. Weak pull-down
(250kΩ).
Buffered Clock Output, Bank A. Weak pull-down
(250kΩ).
3.3V or 2.5V Power Supply.
Power Ground.
Buffered Clock Output, Bank B. Weak pull-down
(250kΩ).
Buffered Clock Output, Bank B. Weak pull-down
(250kΩ).
Select Input, select pin S2. Weak pull-up
(250kΩ).
Select Input, select pin S1. Weak pull-up
(250kΩ).
Buffered Clock Output, Bank B. Weak pull-down
(250kΩ).
Buffered Clock Output, Bank B. Weak pull-down
(250kΩ).
Power Ground.
3.3V or 2.5V Power Supply.
Buffered Clock Output, Bank A. Weak pull-down
(250kΩ).
Buffered Clock Output, Bank A. Weak pull-down
(250kΩ).
PLL Feedback input.
Rev 1.0, May 18, 2006
Page 2 of 15
SL23EP08
General Description-
The SL23EP08 is a low skew, low jitter Zero Delay Buffer
with very low operating current.
The product includes an on-chip high performance PLL that
locks into the input reference clock and produces nine (9)
output clock drivers tracking the input reference clock for
systems requiring clock distribution.
in addition to CLKOUT that is used for internal PLL
feedback, there are two (2) banks with four (4) outputs in
each bank, bringing the number of total available output
clocks to nine (9).
Input and output Frequency Range-
The input and output frequency range is the same. But, the
frequency range depends on VDD and drive levels as given
in the below Table 1.
Select Input Control-
The SL23EP08 provides two (2) input select control pins
called S1 and S2. This feature enables users to selects
various states of output clock banks-A and bank-B, output
source and PLL shutdown features as shown in the Table 2.
The S1 (Pin-9) and S2 (Pin-8) inputs include 250
kΩ weak
pull-down resistors to GND.
PLL Bypass Mode
If the S1 and S2 pins are logic Low(0) and High(1)
respectively, the on-chip PLL is shutdown and bypassed,
and all the nine output clocks bank A, bank B and CLKOUT
clocks are driven by directly from the reference input clock.
In this operation mode SL23EP08 works like a non-ZDB
product.
High and Low-Drive Product Options -
The SL23EP08 is offered with High-Drive “-1H” and
Standard-Drive “-1” options. These drive options enable the
users to control load levels, frequency range and EMI
control. Refer to the AC electrical tables for the details.
Skew and Zero Delay -
If the input clock frequency is less than 2 MHz or floating,
this is detected by an input frequency detection circuitry and
all eight (8) clock outputs are forced to Hi-Z. The PLL is
shutdown to save power. In this shutdown state, the product
draws less than 25 μA supply current.
SpreadThru
™
Feature-
If a Spread Spectrum Clock (SSC) were to be used as an
input clock, the SL23EP08 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from its
reference input to the output clocks. The same spread
characteristics at the input are passed through the PLL and
drivers without any degradation in spread percent (%),
spread profile and modulation frequency
Power Supply Range (VDD)-
The SL23EP08 is designed to operate in a wide power
supply range from 2.3V (Min) to 3.3V (Max). An internal on-
chip voltage regulator is used to supply PLL constant power
supply of 1.8V, leading to a consistent and stable PLL
electrical performance in terms of skew, jitter and power
dissipation. Contact SLI for 1.8V power supply version ZDB
called SL23EPL08.
All outputs should drive the similar load to achieve output-to-
output skew and input-to-output specifications given in the
AC electrical tables. However, Zero delay between input and
outputs can be adjusted by changing the loading of CLKOUT
relative to the banks A and B clocks since CLKOUT is the
feedback to the PLL.
VDD(V)
3.3
3.3
2.5
2.5
Drive
HIGH
STD
HIGH
STD
Min(MHz) Max(MHz)
10
10
10
10
220
167
200
133
Table 1. Input/Output Frequency Range
S2
0
0
1
1
S1
0
1
0
1
Clock A1-A4 Clock B1-B4 CLKOUT
Tri-state
Driven
Driven
[1]
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown and
Bypass
Yes
No
Yes
No
Tri-state
Tri-state
Driven
[1]
Driven
Driven
Driven (4)
Driven
Driven
Driven
Table 2. Select Input Decoding
Rev 1.0, May 18, 2006
Page 3 of 15
SL23EP08
Device
SL23EP08-1
SL23EP08-1H
SL23EP08-2
SL23EP08-2
SL23EP08-3
SL23EP08-3
SL23EP08-4
SL23EP08-5H
Feedback From
Bank-A or Bank-B
Bank-A or Bank-B
Bank-A
Bank-B
Bank-A
Bank-B
Bank-A or Bank-B
Bank-A or Bank-B
Bank-A Frequency
Reference
Reference
Reference
2x Reference
2X Reference
4X Reference
2X Reference
Reference /2
Bank-B Frequency
Reference
Reference
Reference/2
Reference
[2]
Reference
2X Reference
2X Reference
Reference /2
Table 3. Available SL23EP08 Configurations
Notes:
1. Outputs are inverted on SL23EP08-2 and SL23EP08-3 in PLL bypass mode when S2=1 and S1=0.
2. Output phase is either 0° or 180° with respect to CLKIN input. If phase integrity is required, use the SL23EP08-2.
1500
1000
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
Output Load Difference: FBK Load – CLKA or CLKB Load (pF)
Figure 1. CLKIN Input to CLKA and CLKB Delay
Rev 1.0, May 18, 2006
Page 4 of 15
SL23EP08
Absolute Maximum Ratings
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Rating (Human Body Model)
MIL-STD-883, Method 3015
In operation, C-Grade
In operation, I-Grade
No power is applied
In operation, power is applied
Condition
Min.
– 0.5
– 0.5
0
– 40
– 65
–
–
2000
Max.
4.6
VDD+0.5
70
85
150
125
260
–
Unit
V
V
°C
°C
°C
°C
°C
V
Operating Conditions: Unless otherwise stated VDD=2.5V to 3.3V and for both C and I Grades
Symbol Description
Condition
Min.
Max.
VDD3.3
VDD2.5
TA
3.3V Supply Voltage
2.5V Supply Voltage
Operating Temperature(Ambient)
3.3V+/-10%
2.5V+/-10%
Commercial
Industrial
CLOAD
Load Capacitance
<100 MHz, 3.3V with Standard or High
drive
<100 MHz, 2.5V with High drive
<133.3 MHz, 3.3V with Standard or
High drive
<133.3 MHz, 2.5V with High drive
<133.3 MHz, 2.5V with Standard drive
>133.3 MHz, 3.3V with Standard or
High drive
>133.3 MHz, 2.5V with High drive
CIN
CLBW
Input Capacitance
Closed-loop bandwidth
S1, S2 and CLKIN pins
3.3V, (typical)
2.5V, (typical)
ZOUT
Output Impedance
3.3V, (typical), High drive
3.3V, (typical), Standard drive
2.5V, (typical), High drive
2.5V, (typical), Standard drive
3.0
2.3
0
–40
–
–
–
–
–
–
–
–
1.2
0.8
29
41
37
41
3.6
2.7
70
85
30
30
22
22
15
15
15
5
Unit
V
V
°C
°C
pF
pF
pF
pF
pF
pF
pF
pF
MHz
MHz
Ω
Ω
Ω
Ω
Rev 1.0, May 18, 2006
Page 5 of 15
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