EFM8 Busy Bee Family
EFM8BB1 Data Sheet
The EFM8BB1, part of the Busy Bee family of MCUs, is a multi-
purpose line of 8-bit microcontrollers with a comprehensive feature
set in small packages.
These devices offer high-value by integrating advanced analog and communication pe-
ripherals into small packages, making them ideal for space-constrained applications.
With an efficient 8051 core, enhanced pulse-width modulation, and precision analog, the
EFM8BB1 family is also optimal for embedded applications.
EFM8BB1 applications include the following:
• Motor control
• Consumer electronics
• Sensor controllers
• Medical equipment
• Lighting systems
• I/O port expander
KEY FEATURES
• Pipelined 8-bit C8051 core with 25 MHz
maximum operating frequency
• Up to 18 multifunction, 5 V tolerant I/O pins
• One 12-bit Analog to Digital converter
(ADC)
• Two low-current analog comparators
• Integrated temperature sensor
• 3-channel enhanced PWM / PCA
• Four 16-bit timers
• UART, SPI and SMBus/I2C
• Priority crossbar for flexible pin mapping
Core / Memory
CIP-51 8051 Core
(25 MHz)
Flash Program
Memory
(up to 8 KB)
Clock Management
External CMOS
Oscillator
High Frequency
RC Oscillator
Energy Management
Internal LDO
Regulator
Power-On Reset
RAM Memory
(up to 512 bytes)
Debug Interface
with C2
Low Frequency
RC Oscillator
Brown-Out Detector
8-bit SFR bus
Serial Interfaces
UART
SPI
I/O Ports
External
Interrupts
Pin Reset
Timers and Triggers
16-bit
Timers
PCA/PWM
Analog Interfaces
ADC
Analog
Comparators
Security
16-bit CRC
I
2
C / SMBus
General Purpose I/O
Watchdog Timer
Internal Voltage Reference
Lowest power mode with peripheral operational:
Normal
Idle
Shutdown
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EFM8BB1 Data Sheet
Feature List
1. Feature List
The EFM8BB1 highlighted features are listed below.
• Core:
• Pipelined CIP-51 Core
• Fully compatible with standard 8051 instruction set
• 70% of instructions execute in 1-2 clock cycles
• 25 MHz maximum operating frequency
• Memory:
• Up to 8 kB flash memory, in-system re-programmable
from firmware.
• Up to 512 bytes RAM (including 256 bytes standard 8051
RAM and 256 bytes on-chip XRAM)
• Power:
• Internal LDO regulator for CPU core voltage
• Power-on reset circuit and brownout detectors
• I/O: Up to 18 total multifunction I/O pins:
• All pins 5 V tolerant under bias
• Flexible peripheral crossbar for peripheral routing
• 5 mA source, 12.5 mA sink allows direct drive of LEDs
• Clock Sources:
• Internal 24.5 MHz oscillator with ±2% accuracy
• Internal 80 kHz low-frequency oscillator
• External CMOS clock option
• Timers/Counters and PWM:
• 3-channel programmable counter array (PCA) supporting
PWM, capture/compare, and frequency output modes
• 4 x 16-bit general-purpose timers
• Independent watchdog timer, clocked from the low frequen-
cy oscillator
• Communications and Digital Peripherals:
• UART
• SPI™ Master / Slave
• SMBus™/I2C™ Master / Slave
• 16-bit CRC unit, supporting automatic CRC of flash at 256-
byte boundaries
• Analog:
• 12-Bit Analog-to-Digital Converter (ADC)
• 2 x Low-current analog comparators with adjustable refer-
ence
• On-Chip, Non-Intrusive Debugging
• Full memory and register inspection
• Four hardware breakpoints, single-stepping
• Pre-loaded UART bootloader
• Temperature range -40 to 85 ºC
• Single power supply 2.2 to 3.6 V
• QSOP24, SOIC16, and QFN20 packages
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8BB1 devices are truly standalone
system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing non-volatile data storage and allowing field up-
grades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory
and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional
while debugging. Each device is specified for 2.2 to 3.6 V operation, is AEC-Q100 qualified, and is available in 20-pin QFN, 16-pin
SOIC or 24-pin QSOP packages. All package options are lead-free and RoHS compliant.
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EFM8BB1 Data Sheet
Ordering Information
2. Ordering Information
EFM8 BB1 0 F 8 G
–
A
–
QSOP24 R
Tape and Reel (Optional)
Package Type
Revision
Temperature Grade G (-40 to +85)
Flash Memory Size – 8 KB
Memory Type (Flash)
Family Feature Set
Busy Bee 1 Family
Silicon Labs EFM8 Product Line
Figure 2.1. EFM8BB1 Part Numbering
All EFM8BB1 family members have the following features:
• CIP-51 Core running up to 25 MHz
• Two Internal Oscillators (24.5 MHz and 80 kHz)
• SMBus / I2C
• SPI
• UART
• 3-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)
• 4 16-bit Timers
• 2 Analog Comparators
• 12-bit Analog-to-Digital Converter with integrated multiplexer, voltage reference, and temperature sensor
• 16-bit CRC Unit
• AEC-Q100 qualified
• Pre-loaded UART bootloader
In addition to these features, each part number in the EFM8BB1 family has a set of features that vary across the product line. The
product selection guide shows the features available on each family member.
Table 2.1. Product Selection Guide
Digital Port I/Os (Total)
Ordering Part Number
Comparator 0 Inputs
Comparator 1 Inputs
Flash Memory (kB)
RAM (Bytes)
ADC0 Channels
(RoHS Compliant)
Temperature Range
EFM8BB10F8G-A-QSOP24
EFM8BB10F8G-A-QFN20
EFM8BB10F8G-A-SOIC16
EFM8BB10F4G-A-QFN20
EFM8BB10F2G-A-QFN20
8
8
8
4
2
512
512
512
512
256
18
16
13
16
16
16
15
12
15
15
8
8
6
8
8
8
7
6
7
7
Pb-free
Yes
Yes
Yes
Yes
Yes
-40 to +85 C QSOP24
-40 to +85 C QFN20
-40 to +85 C SOIC16
-40 to +85 C QFN20
-40 to +85 C QFN20
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Package
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EFM8BB1 Data Sheet
System Overview
3. System Overview
3.1 Introduction
Power On
Reset
Reset
C2CK/RSTb
Debug /
Programming
Hardware
C2D
CIP-51 8051 Controller
Core
8/4/2 KB ISP Flash
Program Memory
Port I/O Configuration
Digital Peripherals
UART
Timers 0,
1, 2, 3
3-ch PCA
Priority
Crossbar
Decoder
Port 1
Drivers
P1.n
Port 0
Drivers
P0.n
256 Byte SRAM
256 Byte XRAM
I2C /
SMBus
SPI
VDD
GND
Power Net
Independent
Watchdog Timer
SYSCLK
SFR
Bus
CRC
Crossbar Control
Port 2
Driver
P2.n
Analog Peripherals
Internal
Reference
VDD
VREF
VDD
12/10 bit
ADC
AMUX
System Clock
Configuration
24.5 MHz
2%
Oscillator
Low-Freq.
Oscillator
CMOS
Oscillator
Input
Temp
Sensor
EXTCLK
+
-+
-
2 Comparators
Figure 3.1. Detailed EFM8BB1 Block Diagram
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EFM8BB1 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Normal
Idle
Details
Core and all peripherals clocked and fully operational
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
• All internal power nets shut down
• Pins retain state
• Exit on pin or power-on reset
Mode Entry
—
Set IDLE bit in PCON0
Wake-Up Sources
—
Any interrupt
Shutdown
1. Set STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
• RSTb pin reset
• Power-on reset
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.7 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P2.0 and P2.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.0.
•
•
•
•
•
Up to 18 multi-functions I/O pins, supporting digital and analog functions.
Flexible priority crossbar decoder for digital peripheral assignment.
Two drive strength settings for each port.
Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 24.5 MHz oscillator divided by 8.
•
•
•
•
•
Provides clock to core and peripherals.
24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
80 kHz low-frequency oscillator (LFOSC0).
External CMOS clock input (EXTCLK).
Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
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