circuit designed for use in precision, high-speed, data-
acquisition applications.
The circuit employs an input transconductance ampli-
fier capable of providing large amounts of charging
current to the holding capacitor, thus enabling fast
acquisition times. It also incorporates a low leakage
analog switch and an output integrating amplifier with
input bias current optimized to assure low droop rates.
Since the analog switch always drives into a load at
virtual ground, charge injection into the holding ca-
pacitor is constant over the entire input voltage range.
As a result, the charge offset (pedestal voltage) result-
ing from this charge injection can be adjusted to zero
by use of the offset adjustment capability. The device
includes an internal holding capacitor to simplify ease
of application; however, provision is also made to add
additional external capacitance to improve the output
voltage droop rate.
The SHC5320 is manufactured using a dielectric iso-
lation process which minimizes stray capacitance (en-
abling higher-speed operation), and eliminates latch-
up associated with substrate SCRs. The SHC5320KH,
KP, and KU feature fully specified operation over the
extended industrial temperature range of –40°C to
+85°C, while the SHC5320SH operates over the tem-
perature range of –55°C to +125°C. The device re-
quires
±15V
supplies for operation, and is packaged in
a reliable 14-pin ceramic or plastic dual-in-line pack-
age, as well as a 16-pin surface mount plastic package.
APPLICATIONS
q
PRECISION DATA ACQUISITION
SYSTEMS
q
DIGITAL-TO-ANALOG CONVERTER
DEGLITCHER
q
AUTO ZERO CIRCUITS
q
PEAK DETECTORS
External
Hold
Capacitor
100pF
–Input
–
+Input
+
Mode
Control
Reference Bandwidth
Common Control
Output
Offset
Adjust
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
At +25°C, rated power supplies, gain = +1, and with internal holding capacitor, unless otherwise noted.
SHC5320KH, KP, KU
PARAMETERS
INPUT CHARACTERISTICS
ANALOG
Voltage Range
Common-Mode Range
Input Resistance
Input Capacitance
Bias Current
Bias Current Over Temperature Range
Offset Current
Offset Current Over Temperature Range
DIGITAL
(Over Temperature Range)
V
IH
(Logic “1”)
V
IL
(Logic “0”)
I
IH
(V
I
= +5V)
I
IL
(V
I
= 0V)
Logic “0” = SAMPLE
Logic “1” = HOLD
OUTPUT CHARACTERISTICS
Voltage Range
Current
Output Impedance (Hold Mode)
Noise, DC to 10MHz: Sample Hold
Hold Mode
DC ACCURACY/STABILITY
Gain, Open Loop, DC
Input Offset Voltage
Input Offset Voltage Over Temperature Range
Input Offset Voltage Drift
CMRR
(1)
Power Supply Rejection
(2)
: +V
CC
–V
CC
HOLD-TO-SAMPLE MODE
DYNAMIC CHARACTERISTICS
Acquisition Time, A = –1, 10V Step
(3)
:
to
±0.01%
to
±0.1%
SAMPLE MODE
Gain-Bandwidth Product (Gain = +1)
(4)
:
C
H
= 100pF
C
H
= 1000pF
Full Power Bandwidth
(5)
Slew Rate
(6)
Rise Time
(4)
Overshoot
(4)
SAMPLE-TO-HOLD MODE
DYNAMIC CHARACTERISTICS
Aperture Time
(7)
Effective Aperture Time
Aperture Uncertainty (Aperture Jitter)
Charge Offset (Pedestal)
(8)
(Adjustable to Zero)
Charge Transfer
(8)
Sample-to-Hold Transient Settling Time
to
±0.01%
of FSR
HOLD MODE
Droop
(9)
Droop at Maximum Temperature
(9)
Drift Current
(9)
Drift Current at Maximum Temperature
(9)
Feedthrough, 10Vp-p, 100kHz Sinewave
MIN
TYP
MAX
MIN
SHC5320SH
TYP
MAX
UNITS
±10
±10
1
5
±100
±30
3
±300
±300
±300
±300
T
T
T
T
±70
T
T
±200
±200
±100
±100
V
V
MΩ
pF
nA
nA
nA
nA
V
V
µA
µA
2.0
0.8
0.1
4
T
T
T
T
±10
±10
1
125
125
3 x 10
5
2 x 10
6
±0.5
±5
90
200
200
T
T
T
T
T
10
6
±1.5
±20
80
T
T
T
±0.2
T
T
T
T
V
mA
Ω
µVrms
µVrms
V/V
mV
mV
µV/°C
dB
dB
dB
±2
±15
72
80
65
1
0.8
1.5
1.2
T
T
T
T
µs
µs
2
180
600
45
100
15
T
T
T
T
T
T
MHz
kHz
kHz
V/µs
ns
%
–50
25
–25
0.3
1
0.1
165
0.08
1.2
8
0.12
2
0
5
0.5
350
0.5
100
50
10
T
T
T
T
T
T
T
T
17
T
1.7
T
T
T
T
T
T
T
T
T
ns
ns
ns
mV
pC
ns
µV/µs
µV/µs
pA
nA
mV
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
SHC5320
2
SPECIFICATIONS (Cont.)
At +25°C, rated power supplies, gain = +1, and with internal holding capacitor, unless otherwise noted.
SHC5320KH, KP, KU
PARAMETERS
POWER SUPPLIES
+V
CC
–V
CC
+I
CC
(+V
CC
= 15V)
(9)
–I
CC
(–V
CC
= 15V)
(9)
TEMPERATURE
Specification
Storage
PACKAGE
T
Specification the same as SCH5320KH, KP, KU.
NOTES: (1) V
CM
=
±5VDC.
(2) Based on a
±0.5V
swing for each supply with all other supplies held constant. (3) V
O
= 10V step, R
L
= 2kΩ, C
L
= 50pF. (4) V
O
= 200mVp-p,
R
L
= 2kΩ, C
L
= 50pF. (5) V
IN
= 20Vp-p, R
L
= 2kΩ, C
L
= 50pF, unattenuated output. (6) V
O
= 20V step, R
L
= 2kΩ, C
L
= 50pF. (7) Simulated only, not tested. (8) V
IN
=
0V, V
IH
= +3.5V, t
R
< 20ns (V
IL
to V
IH
). (9) Specified for zero differential input voltage between pins 1 and 2. Supply current will increase with differential input (as may
Lead Temperature (soldering, 10s) ................................................. 300°C
CAUTION: These devices are sensitive to electrostatic discharge.
Appropriate I.C. handling procedures should be followed.
NOTES: (1) Absolute maximum ratings are limiting values, applied individually,
beyond which the serviceability of the circuit may be impaired. Functional
operation under any of these conditions is not necessarily implied. Absolute
maximum ratings apply to both dice and package parts, unless otherwise noted.
(2) Internal power dissipation may limit output current to less than +20mA. (3)
WARNING: This device cannot withstand even a momentary short circuit
to either supply.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
163
010
211
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
PACKAGE
MARKING
SHC5320KH
SHC5320KP
SHC5320KU
SHC5320KU
SHC5320SH
ORDERING
NUMBER
(1)
SHC5320KH
SHC5320KP
SHC5320KU
SHC5320KU/1K
SHC5320SH
TRANSPORT
MEDIA
Rail
Rail
Rail
Tape and Reel
Rail
PRODUCT
SHC5320KH
SHC5320KP
SHC5320KU
PACKAGE
CERDIP-14
DIP-14
SO-16
"
SHC5320SH
"
CERDIP-14
"
163
"
–55°C to +125°C
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “SHC5320KU/1K” will get a single 1000-piece Tape and Reel.
®
3
SHC5320
TYPICAL PERFORMANCE CURVES
±V
CC
= 15V.
CHARGE OFFSET
vs MODE CONTROL (V
IH
) VOLTAGE
2.0
C
H
= 100pF
Hold Step Voltage (mV)
1.5
+75°C
TYPICAL SAMPLE/HOLD PERFORMANCE
AS FUNCTION OF HOLDING CAPACITOR
10
5
Acquisition Time (µs)
for 10V Step to ±0.01%
Voltage Droop (mV/100ms)
during Hold Mode
1.0
0.5
1.0
+25°C
0.5
0.1
0.05
Charge Offset
Error (mV)
0.01
100
1000
0
10
C
H
Value (pF)
100
1M
1
2
3
Logic Level High (V)
4
5
OPEN-LOOP GAIN
AND PHASE RESPONSE
120
100
80
–45
0
45
DRIFT CURRENT
vs TEMPERATURE
10k
1k
Phase (degrees)
C
H
= 100pF
I
DRIFT
(pA)
Gain (dB)
60
40
20
0
1
10
100
1k
10k
G
C
H
= 1100pF
θ
C
H
= 100pF
G
100
90
135
180
225
10M
10
1
100k
1M
0
–50
–25
0
25
50
75
100
125
Frequency (Hz)
Temperature (°C)
®
SHC5320
4
DISCUSSION OF
SPECIFICATIONS
WHAT IS A SAMPLE/HOLD AMPLIFIER?
A sample/hold amplifier (also sometimes called a track-and-
hold amplifier) is a circuit that captures and holds an analog
voltage at a specific point in time under control of an
external circuit, such as a microprocessor. This type of
circuit has many applications; however, its primary use is in
data acquisition systems which require that the voltage be
captured and held during the analog-to-digital conversion
process. Use of a sample/hold effectively increases the
bandwidth of a data acquisition system by a significant
amount. For further discussion of this capability, refer to
“Signal Digitization” in the Applications section of this data
sheet.
The ideal sample/hold amplifier in its simplest form contains
four primary components as illustrated in Figure 1, although
in actual practice they may not be internally connected
exactly as shown. Amplifier A
1
, the input buffer, provides a
high impedance load to the source circuit and supplies
charging current to the holding capacitor C
H
. Switch S
1
opens and closes under external control to gate the buffered
input signal to the holding circuit or to remove it so that the
most recently sampled signal will be held. Amplifier A
2
serves to present a high impedance load to the holding
capacitor and to provide a low impedance voltage source for
external loads. A minimum of three terminals are provided
for the user: input, output, and mode control (or sample/hold
control). When S
1
, is closed, the output signal follows the
input signal, subject to errors imposed by amplifier band-
width and other errors as discussed below. When S
1
, is
opened, the voltage stored on the holding capacitor will be
held indefinitely (in the ideal case), and will appear at the
output of the circuit until S
1
, is again closed under command
of the mode control signal.
Settling
Time
Sample-to-Hold
Transient and
Charge Offset
Input
Feed-
though
Output
Slew Rate
Limited
Droop
Aperture
Uncertainty
Acquisition
Aperture Time
Time
Hold
Mode Control
Sample
Settling
Time
Offset
Sample
FIGURE 2. Illustration of Sample/Hold Specifications.
actual acquisition time to be highly dependent on the ampli-
tude of the voltage to be acquired, relative to the value
already held by the capacitor. Therefore, proper specifica-
tion of sample/hold amplifier performance includes defini-
tion of both output value step size and required error band
accuracy.
Aperture Time
(or aperture delay time) is the time required
for switch S
1
, to open and remove the charging signal from
the capacitor after the mode control signal has changed from
“sample” to “hold.” This time is measured from the 50%
point of the Hold mode transition to the time at which the
output stops tracking the input. This parameter is very
important in applications for which the input signal is
changing very rapidly when the Hold mode is initiated.
Effective Aperture Time
is the difference in propagation
delay times of the analog signal and the mode control signal
from their respective input pins to switch S
1
. This time may
be negative, zero, or positive. A negative value indicates that
the mode control propagation delay is shorter than the
analog propagation delay, with the result that the analog
value present on the capacitor at the time the switch opens
occurred earlier than the application of the mode control
signal by the amount of the effective aperture delay time.
Aperture Uncertainty
(or aperture jitter) is the variation
observed in the aperture time over a large number of obser-
vations. This parameter is important when the analog input
is a rapidly changing signal, as aperture uncertainty contrib-
utes to lack of knowledge (at the output) about the true value
of the input at the precise time the Hold mode is initiated.
The maximum input frequency for a given acceptable error
contribution due to aperture uncertainty is
f
MAX
= Maximum Fractional Error/2πt
U
where Maximum Fractional Error (MFE) is the ratio of the
maximum allowable error voltage to peak voltage, and t
U
is
the aperture uncertainty time. For a bipolar
±10V
signal and
a maximum uncertainty error of 1/2LSB in a 12-bit system,
the MFE is equal to 1/2LSB
÷
V
PEAK
= 2.44mV
÷
10V =
0.000244V/V, since 1/2LSB = 2.44mV for a 20V full-scale
range.
For the same system operating with a unipolar 0V to 10V
signal, MFE would be 0.000122V/V.
®
Input
Mode
Control
–
A
1
+
S
1
–
A
2
+
C
H
Output
FIGURE 1. Ideal Sample/Hold Amplifier.
The following discussion of specifications covers the critical
types of errors which may be experienced in applications of
a sample/hold amplifier. These errors are depicted graphi-
cally in Figure 2, and in the Typical Performance Curves.
Acquisition Time
is the time required for the sample/hold
output to settle within a given error band of its final value
after the sample mode is initiated. Included in this time are
effects of switch delay time, slew rate of the buffer ampli-
fier, and settling time for a specified change in held voltage
value. Slew rate limitations of the buffer amplifier will cause
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