CALIFORNIA MICRO DEVICES
XRN772-XXXX
Thin Film Resistor Series
California Micro Devices Hx (Stable Extended Capability
Chip) Series offer exceptional stability and low noise.
Available in the standard center tapped configuration,
they have low electro migration qualities and extremely
low TCR.
Electrical Specifications
Parameter
TCR
TTCR
Op e r a t i n g Vo l t a g e
Powe r Ra t i n g
Derat i on
T h e r m a l S h o ck
Hi g h Te mp e r a t u r e Ex p o s u r e
Mo i s t u r e Re s i s t a n c e
L i fe
Noi se
I nsul at i on Resi st ance
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
@ 7 0 ° C ( D e r a t e l i n e a r l y t o ze r o @ 1 5 0 ° C )
3 0 ° C fo r 2 ye a r s
Me t h o d 1 0 7 MI L - STD- 2 0 2 F
1 0 0 Hr s @ 1 5 0 ° C Amb i e n t
Me t h o d 1 0 6 MI L - STD- 2 0 2 F
Me t h o d 1 0 8 MI L - STD- 2 0 2 F ( 1 2 5 ° C/ 1 0 0 0 h r )
Me t h o d 3 0 8 MI L - STD- 2 0 2 F u p t o 2 5 0 K
Ω
≥
250K
Ω
@2 5 ° C
Conditions
±100ppm
± 5 p p m/ ° C
100Vdc
1 2 5 mw
± 0 . 1 %
∆
± 0 . 2 %
∆R
±0.15%
± 0 . 2 %
∆R
± 0 . 2 %
∆R
–35dB
–20dB
1 X 1 0
12
Ω
Ma x
Ma x
Ma x
Ma x
Ma x
Ma x
Ma x
Ma x
Ma x
Ma x
Mi n
Bonding Area
Va l u e s
20M
Ω
to 60M
Ω
standard. Standard ratio tolerance between
resistors = ±1%. Tighter ratio tolerance available.
R
1
R
2
Laser Code Area
Formats
Die Size: 60±3 mils square
Bonding Pads: 4x4 mils typical
Substrate
Isolation Layer
Resistor
Backing
Bond Pads
Mechanical Specifications
Silicon 10±2 mils thick
Si0
2
10,000Å thick, min
Proprietary Silicon Chrome
Lapped (gold optional)
Aluminum 10,000Å thick, min
20 MΩ to 60 MΩ
Ω
Ω
Notes
1. Code boxes are available for alphanumeric laser
marking on the chip.
2. Resistor pattern may vary from one value to another.
Pa ck a g i n g
Two inch square trays of 100 chips maximum is standard.
Pa r t N u m b e r D e s i g n a t i o n
XRN772
Series
2005
Resistance Value
Fi rst 3 di gi t s are
si gni fi cant
va l u e .
Last di gi t
represents
nu mb e r o f
ze r o s.
R i ndi cates
d e c i ma l p o i n t .
F
Tolerance
F = ±1%
G = ±2%
TCR
No Let t er = ±100ppm
A = ±50ppm
A
G
Bond Pads
G = Gol d
No Let t er =
Al u mi nu m
W
Backing
W = Gol d
L = Lapped
No Let t er =
Ei t her
P
Ratio Tolerance
St d = ±1%
P = ±0.5%
J = ±5%
K = ±10%
B = ±25ppm
© 2000 California Micro Devices Corp. All rights reserved.
8/9/2000
C1370800
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
