SiT1602
Low Power, Standard Frequency Oscillator
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
51 standard frequencies between 3.75 MHz and 77.76 MHz
100% pin-to-pin drop-in replacement to quartz-based XO
Excellent total frequency stability as low as ±20 PPM
Low power consumption of 3.6 mA typical
Standby mode for longer battery life
Fast startup time of 5 ms
LVCMOS/HCMOS compatible output
Industry-standard packages: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2,
7.0 x 5.0 mm x mm
Instant samples with
Time Machine II
and
field programmable
oscillators
Pb-free, RoHS and REACH compliant
Ideal for DSC, DVC, DVR, IP CAM, Tablets, e-Books, SSD,
GPON, EPON, etc
Ideal for high-speed serial protocols such as: USB, SATA, SAS,
Firewire, 100M / 1G / 10G Ethernet, etc.
Electrical Characteristics
[1]
Parameter and Conditions
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
Typ.
Max.
Unit
MHz
PPM
PPM
PPM
°C
°C
V
V
V
V
V
V
mA
mA
mA
mA
mA
A
A
A
%
ns
ns
ns
Vdd
No load condition, f = 20 MHz, Vdd = 2.8V to 3.3V
No load condition, f = 20 MHz, Vdd = 2.5V
No load condition, f = 20 MHz, Vdd = 1.8V
Vdd = 2.5V to 3.3V, OE = GND, output is Weakly Pulled Down
Vdd = 1.8 V. OE = GND, output is Weakly Pulled Down
ST = GND, Vdd = 2.8V to 3.3V, Output is Weakly Pulled Down
ST = GND, Vdd = 2.5V, Output is Weakly Pulled Down
ST = GND, Vdd = 1.8V, Output is Weakly Pulled Down
All Vdds
Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%
Vdd =1.8V, 20% - 80%
Vdd = 2.25V - 3.63V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Pin 1, OE or ST
Pin 1, OE or ST
Pin 1, OE logic high or logic low, or ST logic high
Pin 1, ST logic low
Condition
51 standard frequencies between 3.75 MHz and 77.76 MHz
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load.
Frequency Range
(Refer
to the frequency list page 10)
-20
-25
-50
Operating Temperature Range
T_use
-20
-40
Supply Voltage
Vdd
1.62
2.25
2.52
2.7
2.97
2.25
Current Consumption
Idd
–
–
–
OE Disable Current
Standby Current
I_OD
I_std
–
–
–
–
–
Duty Cycle
Rise/Fall Time
DC
Tr, Tf
45
–
–
–
Output High Voltage
VOH
90%
–
–
–
–
–
1.8
2.5
2.8
3.0
3.3
–
3.8
3.6
3.4
–
–
2.6
1.4
0.6
–
1
1.3
–
–
+20
+25
+50
+70
+85
1.98
2.75
3.08
3.3
3.63
3.63
4.5
4.2
3.9
4
3.8
4.3
2.5
1.3
55
2
2.5
2
–
Frequency Stability and Aging
Operating Temperature Range
Extended Commercial
Industrial
Contact
SiTime
for 1.5V support
Supply Voltage and Current Consumption
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input High Voltage
Input Low Voltage
Input Pull-up Impedence
VIH
VIL
Z_in
70%
–
–
2
–
–
87
–
–
30%
100
–
Vdd
Vdd
k
M
Note:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
SiTime Corporation
Rev. 1.2
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised March 26, 2015
SiT1602
Low Power, Standard Frequency Oscillator
The Smart Timing Choice
The Smart Timing Choice
Electrical Characteristics
[1]
(continued)
Parameter and Conditions
Startup Time
Enable/Disable Time
Resume Time
Startup Time
RMS Period Jitter
RMS Phase Jitter (random)
Symbol
T_start
T_oe
T_resume
T_start
T_jitt
T_phj
Min.
–
–
–
–
–
–
–
–
Typ.
–
–
–
–
1.76
1.78
0.5
1.3
Max.
5
130
5
5
Jitter
3
3
0.9
2
ps
ps
ps
ps
f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 75 MHz, Vdd = 1.8V
f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz
Unit
ms
ns
ms
ms
Condition
Measured from the time Vdd reaches its rated minimum value
f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles
Measured from the time ST pin crosses 50% threshold
Measured from the time Vdd reaches its rated minimum value
Startup and Resume Timing
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
Pin Description
Pin
Symbol
OE/ ST
1
22
Output
Enable
Standby
GND
OUT
VDD
Power
Output
Power
[2]
Functionality
H or Open : specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open
[2]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
Electrical ground
[3]
Oscillator output
Power supply voltage
[3]
GND
2
Top View
OE/ST
1
4
VDD
2
3
4
3
OUT
Notes:
2. A pull-up resistor of <10 k between OE/ ST pin and Vdd is recommended in high noise environment.
3. A capacitor value of 0.1 µF between Vdd and GND is required.
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Thermal Consideration
Package
7050
5032
3225
2520
2016
JA, 4 Layer Board
(°C/W)
191
97
109
117
124
JA, 2 Layer Board
(°C/W)
263
199
212
222
227
JC, Bottom
(°C/W)
30
24
27
26
26
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.2
Page 2 of 11
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SiT1602
Low Power, Standard Frequency Oscillator
The Smart Timing Choice
The Smart Timing Choice
Test Circuit and Waveform
[4]
Vdd
Vout
Test
Point
tr
80% Vdd
tf
4
Power
Supply
0.1µF
3
15pF
(including probe
and fixture
capacitance)
50%
20% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
1
2
Vdd
OE/ST Function
1k
Figure 1. Test Circuit
Note:
4. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 2. Waveform
Timing Diagram
90% Vdd, 2.5/2,8/3.3V devices
Vdd
95% Vdd, 1.8V devices
Vdd
Pin 4 Voltage
NO Glitch first cycle
ST Voltage
50% Vdd
T_resume
CLK Output
T_start
CLK Output
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 3. Startup Timing (OE/ST Mode)
u
Vdd
50% Vdd
T_OE
CLK Output
Figure 4. Standby Resume Timing (ST Mode Only)
OE Voltage
Vdd
OE Voltage
50% Vdd
CLK Output
T_OE
HZ
T_OE: Time to re-enable the clock output
T_OE: Time to put the output drive in High Z mode
Figure 5. OE Enable Timing (OE Mode Only)
Figure 5. OE Disable Timing (OE Mode Only)
Notes:
5. SiT1602 supports “no runt” pulses and “no glitch” output during startup or resume.
6. SiT1602 supports gated output which is accurate within rated frequency stability from the first cycle.
Rev. 1.2
Page 3 of 11
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SiT1602
Low Power, Standard Frequency Oscillator
The Smart Timing Choice
The Smart Timing Choice
Performance Plots
1.8
5.0
4.8
4.6
4.4
2.5
2.8
3
3.3
4.0
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
RMS period jitter (ps)
0
10
20
30
40
50
60
70
80
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
10
20
30
40
50
60
70
80
IDD (mA)
4.2
4.0
3.8
3.6
3.4
3.2
3.0
Frequency (MHz)
Frequency (MHz)
Figure 7. IDD vs Frequency
Figure 8. RMS Period Jitter vs Frequency
1.8 V
2.0
1.8
2.5 V
2.8 V
3.0 V
3.3 V
0.9
0.8
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
IPJ (ps)
1.6
1.4
1.2
1.0
10
20
30
40
50
60
70
80
IPJ (ps)
0.7
0.6
0.5
0.4
10
20
30
40
50
60
70
80
Frequency (MHz)
Frequency (MHz)
Figure 9. RMS Phase Jitter vs Frequency
(12 kHz to 20 MHz Integration Bandwidth)
Figure 10. RMS Phase Jitter vs Frequency
(900 kHz to 20 MHz Integration Bandwidth)
1.8 V
55
54
53
2.5 V
2.8 V 3.0 V
3.3 V
1.8 V
2.5
2.5 V
2.8 V
3.0 V
3.3 V
Duty Cycle (%)
52
51
50
49
48
47
46
45
0
10
20
30
40
50
60
70
80
Rise Time (ns)
2.0
1.5
1.0
0.5
0.0
-40
-15
10
35
60
85
Frequency (MHz)
Temperature (°C)
Figure 11. Duty Cycle vs Frequency
Figure 12. Rise Time vs Temperature, 20 MHz Output
Note:
7. All plots are measured with 15 pF load at room temperature, unless otherwise stated.
Rev. 1.2
Page 4 of 11
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SiT1602
Low Power, Standard Frequency Oscillator
The Smart Timing Choice
The Smart Timing Choice
Programmable Drive Strength
The SiT1602 includes a programmable drive strength feature
to provide a simple, flexible tool to optimize the clock rise/fall
time for specific applications. Benefits from the programmable
drive strength feature are:
• Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time
• Improves the downstream clock receiver’s (RX) jitter by de-
creasing (speeding up) the clock rise/fall time.
• Ability to drive large capacitive loads while maintaining full
swing with sharp edge rates.
For more detailed information about rise/fall time control and
drive strength selection, see the SiTime Applications Note
section;
http://www.sitime.com/support/application-notes.
EMI Reduction by Slowing Rise/Fall Time
Figure 13 shows the harmonic power reduction as the rise/fall
times are increased (slowed down). The rise/fall times are
expressed as a ratio of the clock period. For the ratio of 0.05,
the signal is very close to a square wave. For the ratio of 0.45,
the rise/fall times are very close to near-triangular waveform.
These results, for example, show that the 11th clock harmonic
can be reduced by 35 dB if the rise/fall edge is increased from
5% of the period to 45% of the period.
10
0
trise=0.05
trise=0.1
trise=0.15
trise=0.2
trise=0.25
trise=0.3
trise=0.35
trise=0.4
trise=0.45
choose to speed up the rise/fall time to 1.68ns by then
increasing the drive strength setting on the SiT1602.
The SiT1602 can support up to 60 pF or higher in maximum
capacitive loads with up to 3 additional drive strength settings.
Refer to the
Rise/Tall Time Tables
to determine the proper
drive strength for the desired combination of output load vs.
rise/fall time
SiT1602 Drive Strength Selection
Tables 1 through 5 define the rise/fall time for a given capac-
itive load and supply voltage.
1. Select the table that matches the SiT1602 nominal supply
voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V).
2. Select the capacitive load column that matches the appli-
cation requirement (5 pF to 60 pF)
3. Under the capacitive load column, select the desired
rise/fall times.
4. The left-most column represents the part number code for
the corresponding drive strength.
5. Add the drive strength code to the part number for ordering
purposes.
Calculating Maximum Frequency
Based on the rise and fall time data given in Tables 1 through
4, the maximum frequency the oscillator can operate with
guaranteed full swing of the output voltage over temperature
as follows:
M a x F re q u e n c y =
1
5 x T rf_ 2 0 /8 0
Harmonic amplitude (dB)
-10
-20
-30
-40
-50
-60
-70
-80
1
3
5
7
9
Where Trf_20/80 is the typical rise/fall time at 20% to 80%
Vdd
Example 1
11
Harm onic num ber
Calculate f
MAX
for the following condition:
• Vdd = 1.8V (Table 1)
• Capacitive Load: 30 pF
• Desired Tr/f time = 3 ns (rise/fall time part number code = E)
Part number for the above example:
SiT1602AIE12-18E-66.666660
Figure 13. Harmonic EMI reduction as a Function of
Slower Rise/Fall Time
Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the
downstream chipset. One way to reduce this jitter is to
increase rise/fall time (edge rate) of the input clock. Some
chipsets would require faster rise/fall time in order to reduce
their sensitivity to this type of jitter. The SiT1602 provides up
to 3 additional high drive strength settings for very fast rise/fall
time. Refer to the
Rise/Fall Time Tables
to determine the
proper drive strength.
High Output Load Capability
The rise/fall time of the input clock varies as a function of the
actual capacitive load the clock drives. At any given drive
strength, the rise/fall time becomes slower as the output load
increases. As an example, for a 3.3V SiT1602 device with
default drive strength setting, the typical rise/fall time is 1ns for
15 pF output load. The typical rise/fall time slows down to
2.6ns when the output load increases to 45 pF. One can
Drive strength code is inserted here. Default setting is “-”
Rev. 1.2
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