WF128K16, WF256K16-XCX5
5V FLASH MODULE
FEATURES
s
Access Times of 50, 60, 70, 90, 120 and 150ns
s
40 pin Ceramic DIP (Package 303)
s
Organized as 128Kx16 and 256Kx16
s
Sector Architecture
• 8 equal size sectors of 16KBytes each per chip
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
s
100,000 Erase/Program Cycles Minimum (0°C to 70°C)
s
Data Retention, 10 Years at 125°C
s
Commercial, Industrial and Military Temperature Ranges
s
5 Volt Programming; 5V
±10%
Supply
s
Low Power CMOS
s
Embedded Erase and Program Algorithms
s
TTL Compatible Inputs and CMOS Outputs
s
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s
Page Program Operation and Internal Program Control Time
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note: Programming information available upon request.
PRELIMINARY *
FIG. 1
PIN CONFIGURATION AND BLOCK DIAGRAM
TOP VIEW
CS2*/NC
CS1
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
GND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE
PIN DESCRIPTION
V
CC
WE
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
0
-
16
I/O
0-15
CS
1
-
2
OE
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
7
BLOCK DIAGRAM
FOR WF256K16-XCX5
I/O
0-7
WE
OE
A
0-16
I/O
8-15
FLASH MODULES
*
CS
2
for 256Kx16 and NC for 128Kx16
BLOCK DIAGRAM
FOR WF128K16-XCX5
I/O
0-7
WE
OE
A
0-16
I/O
8-15
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
CS
1
(1)
CS
2
(1)
CS
1
NOTE:
1. CS
1
and CS
2
are used to select the lower and upper 128Kx16 of the
device. CS
1
and CS
2
must not be enabled at the same time.
October 1998
1
White Microelectronics • Phoenix, AZ • (602) 437-1520
WF128K16, WF256K16-XCX5
ABSOLUTE MAXIMUM RATINGS (1)
Parameter
Operating Temperature
Supply Voltage Range (V
CC
)
Signal voltage range (any pin except A9) (2)
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
Data Retention Mil Temp
Endurance (write/erase cycles) Mil Temp
A
9
Voltage for sector protect (V
ID
) (3)
-55 to +125
-2.0 to +7.0
-2.0 to +7.0
-65 to +150
+300
10 years
10,000 cycles min.
-2.0 to +14.0
V
Unit
°C
V
V
°C
°C
Test
OE capacitance
WE capacitance
CS capacitance
I/O
0-7
capacitance
Address capacitance
CAPACITANCE
(T
A
= 25°C)
Symbol
C
OE
C
WE
C
CS
C
I/O
C
AD
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
Max
50
50
30
30
50
Unit
pF
pF
pF
pF
pF
This parameter is guaranteed by design but not tested.
NOTES:
1. Stresses above the absolute maximum rating may cause permanent damage
to the device. Extended operation at the maximum levels may degrade
performance and affect reliability.
2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions,
inputs may overshoot V
SS
to -2.0 V for periods of up to 20ns. Maximum DC
voltage on output and I/O pins is V
CC
+ 0.5V. During voltage transitions,
outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns.
3. Minimum DC input voltage on A
9
pin is -0.5V. During voltage transitions, A
9
may
overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A
9
is +13.5V which may overshoot to 14.0 V for periods up to 20ns.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
A
9
Voltage for Sector Protect
Symbol
V
CC
V
IH
V
IL
T
A
T
A
V
ID
Min
4.5
2.0
-0.5
-55
-40
11.5
Max
5.5
V
CC
+ 0.3
+0.8
+125
+85
12.5
Unit
V
V
V
°C
°C
V
DC CHARACTERISTICS - CMOS COMPATIBLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Active Current for Read (1)
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
CC3
V
OL
V
OH1
V
OH2
V
LKO
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IL
, OE = V
IH
CS = V
IL
, OE = V
IH
V
CC
= 5.5, CS = V
IH
, f = 5MHz
I
OL
= 12.0 mA, V
CC
= 4.5
I
OH
= -2.5 mA, V
CC
= 4.5
I
OH
= -100
µA,
V
CC
= 4.5
0.85xVcc
V
CC
-0.4
3.2
128K x 16
Min
Max
10
10
70
100
6
0.45
0.85xVcc
V
CC -0.4
3.2
256K x 16
Min
Max
10
10
80
110
8
0.45
µA
µA
mA
mA
mA
V
V
V
V
Unit
7
FLASH MODULES
V
CC
Active Current for Program
or Erase (2)
V
CC
Standby Current
Output Low Voltage
Output High Voltage
Output High Voltage
Low V
CC
Lock Out Voltage
NOTES:
1. The I
CC
current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
White Microelectronics • Phoenix, AZ • (602) 437-1520
2
WF128K16, WF256K16-XCX5
PRINCIPLES OF OPERATION
The following principles of operation of the WF128K16-XCX5
and WF256K16-XCX5 are applicable to each 128K x 8 memory
chip inside the MCM. Programming of the device is accom-
plished by executing the program command sequence. The
program algorithm, which is an internal algorithm, automati-
cally times the program pulse widths and verifies proper cell
margin. Sectors can be programmed and verified in less than 0.3
seconds. Erase is accomplished by executing the erase
command sequence. The erase algorithm, which is internal,
automatically preprograms the array if it is not already
programmed before executing the erase operation. During
erase, the device automatically times the erase pulse widths
and verifies proper cell margin. The entire memory is typically
erased and verified in three seconds (including pre-program-
ming).
WRITE
Device erasure and programming are accomplished via the
command register. The contents of the register serve as input
to the internal state machine. The state machine outputs
dictate the function of the device.
The command register itself does not occupy an addressable
memory location. The register is a latch used to store the
commands, along with address and data information needed to
execute the command. The command register is written by
bringing Write-Enable to a logic-low level (V
IL
), while Chip-Select
is low and OE is at V
IH
. Addresses are latched on the falling edge
of the Write-Enable while data is latched on the rising edge of the
WE pulse. Standard microprocessor write timings are used. Refer
to AC Program characteristics, Figures 4 and 7.
BUS OPERATIONS
READ
The device has two control functions, both of which must be
logically active, to obtain data at the outputs. Chip-Select (CS)
is the power control and should be used for device selection.
Output-Enable (OE) is the output control and should be used to
gate data to the output pins. Figure 3 illustrates read timing
waveforms.
OUTPUT DISABLE
With Output-Enable at a logic-high level (V
IH
), output from the
device is disabled. Output pins are placed in a high
impedance state.
STANDBY MODE
The device has two standby modes, a CMOS standby mode (CS
input held at V
CC
+ 0.5V), and a TTL standby mode (CS is held
V
IH
). In the standby mode the outputs are in a high impedance
state, independent of the OE input.
If the device is deselected during erasure or programming, the
device will draw active current until the operation is completed.
Operation
Read
Standby
Output Disable
Write
Enable Sector Protect
Verify Sector Protect
7
FLASH MODULES
TABLE 1 - BUS OPERATIONS
CS
L
H
L
L
L
L
OE
L
X
H
H
V
ID
L
WE
H
X
H
L
L
H
A
0
A
0
X
X
A
0
X
L
A
1
A
1
X
X
A
1
X
H
A
9
A
9
X
X
A
9
V
ID
V
ID
I/O
D
OUT
HIGH Z
HIGH Z
D
IN
X
Code
3
White Microelectronics • Phoenix, AZ • (602) 437-1520
WF128K16, WF256K16-XCX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Symbol
Min
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (min)
Chip and Sector Erase Time
Read Recovery Time Before Write
V
CC
Setup Time
Chip Programming Time
Output Enable Setup Time
Output Enable Hold Time (1)
1. For Toggle and Data Polling.
t
OES
t
OEH
0
10
t
AVAV
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHEH
t
WHWL
t
WHWH1
t
WHWH2
t
GHWL
t
VCS
t
WC
t
CS
t
WP
t
AS
t
DS
t
DH
t
AH
t
CH
t
WPH
50
0
25
0
25
0
40
0
20
14
2.2
0
50
12.5
0
10
60
-50
Max
-60
Min
60
0
30
0
30
0
45
0
20
14
2.2
0
50
12.5
0
10
60
Max
Min
70
0
35
0
30
0
45
0
20
14
2.2
0
50
12.5
0
10
60
-70
Max
-90
Min
90
0
45
0
45
0
45
0
20
14
2.2
0
50
12.5
0
10
60
Max
-120
Min
120
0
50
0
50
0
50
0
20
14
2.2
0
50
12.5
0
10
60
Max
-150
Min
150
0
50
0
50
0
50
0
20
14
2.2
0
50
12.5
60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
µs
sec
ns
ns
Unit
AC CHARACTERISTICS – READ ONLY OPERATIONS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle Time
Symbol
Min
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
0
50
50
50
25
20
20
0
-50
Max
Min
60
60
60
30
20
20
0
-60
Max
70
70
70
35
20
20
0
-70
Min
Max
90
90
90
40
25
25
0
-90
Min Max
-120
Min
120
120
120
50
30
30
0
Max
-150
Min
150
150
150
55
35
35
Max
ns
ns
ns
ns
ns
ns
ns
Unit
7
FLASH MODULES
Address Access Time
Chip Select Access Time
OE to Output Valid
Chip Select to Output High Z (1)
OE High to Output High Z (1)
Output Hold from Address, CS or OE Change,
whichever is first
1. Guaranteed by design, not tested.
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
WF128K16, WF256K16-XCX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle Time
WE Setup Time
CS Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
WE Hold from WE High
CS Pulse Width High
Duration of Programming Operation
Duration of Erase Operation
Read Recovery before Write
Chip Programming Time
Symbol
t
AVAV
t
WLEL
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHWH
t
EHEL
t
WHWH1
t
WHWH2
t
GHEL
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
WH
t
CPH
50
0
25
0
25
0
40
0
20
14
2.2
0
12.5
60
-50
Min
Max
Min
60
0
30
0
30
0
45
0
20
14
2.2
0
12.5
60
-60
Max
70
0
35
0
30
0
45
0
20
14
2.2
0
12.5
60
-70
Min
Max Min
90
0
45
0
45
0
45
0
20
14
2.2
0
12.5
60
-90
Max
-120
Min
120
0
50
0
50
0
50
0
20
14
2.2
0
12.5
60
Max
-150
Min
150
0
50
0
50
0
50
0
20
14
2.2
0
12.5
60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
sec
Unit
7
FLASH MODULES
FIG. 2
AC TEST CIRCUIT
Current Source
I
OL
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
D.U.T.
V
Z
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
≈
1.5V
Output Timing Reference Level
C
eff
= 50 pf
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
5
White Microelectronics • Phoenix, AZ • (602) 437-1520
京公网安备 11010802033920号
EEWORLD
