K6F1008S2A Family
Document Title
128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
1.0
History
Design target
Finalize
- Change V
DR
: 1.0 to 1.5V
- Change I
DR
test condition : V
CC
=1.2 to 1.5V
Draft Data
November 3, 1998
February 26, 1999
Remark
Advance
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
February 1999
K6F1008S2A Family
CMOS SRAM
128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM
FEATURES
•
•
•
•
•
•
GENERAL DESCRIPTION
The K6F1008S2A families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
industrial temperature range and have various package types
for user flexibility of system design. The families also support
low data retention voltage for battery back-up operation with low
data retention current.
Process Technology: Full CMOS
Organization: 128K x8 bit
Power Supply Voltage: 2.3~2.7V
Low Data Retention Voltage: 1.5V(Min)
Three state output status and TTL Compatible
Package Type: 32-TSOP1-0813.4F
48-FBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
Standby
(I
SB1
, Typ.)
0.5µA
Operating
(I
CC1
, Max)
3mA
PKG Type
K6F1008S2A-I
Industrial(-40~85°C)
2.3~2.7V
70
1)
/100ns
32-sTSOP1-F
48-FBGA
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
A
B
C
D
E
F
G
H
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
32-sTSOP
Type1-Forward
Row
select
Memory array
1024 rows
128×8 columns
2
3
4
5
A
0
I/O
5
I/O
6
V
SS
V
CC
I/O
7
I/O
8
A
9
A
1
A
2
CS
2
WE
NC
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
I/O
2
I/O
1
V
CC
V
SS
NC
OE
A
10
CS
1
A
11
NC
A
16
A
12
A
15
A
13
I/O
3
I/O
4
A
14
I/O
8
Data
cont
I/O Circuit
Column select
Data
cont
48-CSP - TOP VIEW
CS
1
Name
Function
Name
Function
CS
2
WE
OE
Control
logic
CS
1
, CS
2
Chip Select Inputs
OE
WE
A
0
~A
16
Output Enable Input
Write Enable Input
Address Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
Vcc
Vss
N.C.
Power
Ground
No Connection
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
Revision 1.0
February 1999
K6F1008S2A Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
K6F1008S2A-YI70
K6F1008S2A-YI10
K6F1008S2A-FI70
K6F1008S2A-FI10
Function
32-sTSOP1-F, 70ns, 2.5V
32-sTSOP1-F, 100ns, 2.5V
CMOS SRAM
48-FBGA with 48 ball, 70ns, 2.5V
48-FBGA with 48 ball, 100ns, 2.5V
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care (Must be high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.2 to 3.0V
-0.2 to 3.6V
1.0
-55 to 150
-40 to 85
Unit
V
V
W
°C
°C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 1.0
February 1999
K6F1008S2A Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Note :
1. T
A
=-40 to 85°C, otherwise specified
2. Overshoot: Vcc+1.0V in case of pulse width
≤
20ns.
3. Undershoot: -1.0V in case of pulse width
≤
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CMOS SRAM
Symbol
Vcc
Vss
V
IH
V
IL
Min
2.3
0
2.0
-0.2
3)
Typ
2.5
0
-
-
Max
2.7
0
Vcc+0.2
2)
0.4
Unit
V
V
V
V
CAPACITANCE
1)
(f=1MHz, TA=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
Cycle time=1µs, 100%duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
Test Conditions
Min Typ Max Unit
-1
-1
-
-
-
-
2.0
-
-
-
-
-
-
-
-
-
-
0.5
1
1
2
3
20
0.4
-
0.3
3
1)
µA
µA
mA
mA
mA
V
V
mA
µA
I
OL
=0.5mA
I
OH
=-0.5mA
CS
1
=V
IH
, CS2=V
IL
, Other inputs=V
IH
or V
IL
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V,
Other inputs=0~Vcc
1. Super low power product=1µA with special handling.
Revision 1.0
February 1999
K6F1008S2A Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.1V
Output load (See right): C
L
= 100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
V
TM
3)
R
1
2)
C
L
1)
R
2
2)
1. Including scope and jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=2.3V
AC CHARACTERISTICS
(Vcc=2.3~2.7V, T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
70
-
-
-
10
5
0
0
10
70
60
0
60
55
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
Min
100
-
-
-
10
5
0
0
15
100
80
0
80
70
0
0
40
0
5
100ns
Max
-
100
100
50
-
-
30
30
-
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
CS
1
≥Vcc-0.2V
1)
Vcc=1.5V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Test Condition
Min
1.5
-
0
tRC
Typ
-
-
-
-
Max
2.7
1
-
-
Unit
V
µA
ms
1. CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or CS
2
≤0.2V(CS
2
controlled)
Revision 1.0
February 1999