TCP-3039H
Advance Information
3.9 pF Passive Tunable
Integrated Circuits (PTIC)
Introduction
ON Semiconductor’s PTICs have excellent RF performance and
power consumption, making them suitable for any mobile handset or
radio application. The fundamental building block of our PTIC
product line is a tunable material called ParaScant, based on Barium
Strontium Titanate (BST). PTICs have the ability to change their
capacitance from a supplied bias voltage generated by the Control IC.
The 3.9 pF PTICs are available as wafer-level chip scale packages
(WLCSP) and in QFN packages for easy mounting directly on printed
circuit boards.
Key Features
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WLCSP
10 pillar
CASE TBD
QFN
6 pin
CASE TBD
•
•
•
•
•
•
•
•
•
•
•
•
•
High Tuning Range and Operation up to 20 V
Usable Frequency Range: from 700 MHz to 2.7 GHz
High Quality Factor (Q) for Low Loss
High Power Handling Capability
Compatible with PTIC Control IC TCC-103
WLCSP Package: 0.722 x 1.029 x 0.611 mm (10 pillar)
QFN Package: 1.200 x 1.600 x 0.950 mm
QFN: MSL−2 Moisture Sensitivity Level (per J−STD−020)
Pb−Free and RoHS Compliant
Multi-band, Multi-standard, Advanced and Simple Mobile Phones
Tunable Antenna Matching Networks
Tunable RF Filters
Active Antennas
QFN MARKING DIAGRAM
X.XH
X.X = 3.9
H = High Tuning
FUNCTIONAL BLOCK DIAGRAM
PTIC
RF1
RF2
Typical Applications
Bias
Figure 1. PTIC Functional Block Diagram
ORDERING INFORMATION
Device
TCP−3039H−DT
TCP−3039H−QT
Package
WLCSP
(Pb−Free)
QFN
(Pb−Free)
Shipping
4000 Units /
7” Reel
8000 Units /
13” Reel
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
For detailed ordering information, including part
number definition and capacitance (pF) see the
package dimensions section on page 7 of this
datasheet.
©
Semiconductor Components Industries, LLC, 2013
May, 2013
−
Rev. P2
1
Publication Order Number:
TCP−3039H/D
TCP−3039H
TYPICAL SPECIFICATIONS
Representative Performance Data at 255C
Table 1. PERFORMANCE DATA
Parameter
Operating Bias Voltage
Capacitance (V
bias
= 2 V)
Capacitance (V
bias
= 20 V)
Tuning Range (2 V - 20 V)
Tuning Range (20 V - 2 V)
Leakage Current (WLCSP)
Operating Frequency
Quality Factor @ 700 MHz, 10 V
Quality Factor @ 2.4 GHz, 10 V
IP3 (V
bias
= 2 V)
[1,3]
IP3 (V
bias
= 20 V)
[1,3]
2nd Harmonic (V
bias
= 2 V)
[2,3]
2nd Harmonic (V
bias
= 20 V)
[2,3]
3rd Harmonic (V
bias
= 2 V)
[2,3]
3rd Harmonic (V
bias
= 20 V)
[2,3]
Transition Time (Cmin
³
Cmax)
[4]
Transition Time (Cmax
³
Cmin)
[4]
1.
2.
3.
4.
f
1
= 850 MHz, f
2
= 860 MHz, Pin 25 dBm/Tone
850 MHz, Pin +34 dBm
IP3 and Harmonics are measured in the shunt configuration in a 50
W
environment
RF
IN
and RF
OUT
are both connected to DC ground
700
90
60
70
85
-65
-80
-40
-70
80
70
dBm
dBm
dBm
dBm
dBm
dBm
ms
ms
Min
2.0
3.51
0.98
3.40
3.90
1.03
3.80
3.60
2.0
2700
mA
MHz
Typ
Max
20
4.29
1.08
4.20
Units
V
pF
pF
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2
TCP−3039H
Representative performance data at 255C for 3.9 pF WLCSP Package
Figure 2. Capacitance
Figure 3. Harmonic Power*
Figure 4. IP3*
Figure 5. Q*
*The data shown is based on the TCP−1039N device performance, for reference only. The TCP−3039H performance data will be available in
the Production Datasheet.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Input Power
Bias Voltage
Operating Temperature Range
Storage Temperature Range
ESD
−
Human Body Model
Rating
+40
+25 (Note 5)
−30
to +85
−55
to +125
Class 1A JEDEC HBM Standard (Note 6)
Units
dBm
V
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
5. WLCSP: Recommended Bias Voltage not to exceed 20 V
6. Class 1A defined as passing 250 V, but may fail after exposure to 500 V ESD pulse
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3
TCP−3039H
PACKAGE INFORMATION
QFN Package Layout and Dimensional Information
PIN #1 ID
0.100 X 45°
Chamfer
3X 0.250 mm
1.200 mm
±0.050
mm
0.950 mm
±0.050
mm
3X 0.700 mm
2X 0.300 mm
1.600 mm
±0.050
mm
4X 0.500 mm
Bias
RF2
RF2
N/C
RF1
RF1
TOP VIEW
(Note: X.X reflects the PTIC value
e.g.: 3.9 indicates 3.9 pF)
X.XH
0.000 mm / 0.050 mm
SIDE VIEW
3X 0.200 mm
6X 0.575 mm
6X 0.300 mm
0.475 mm
Bias
N/C
RF1
RF1
6X 0.250 mm
±0.030
mm
4X 0.175 mm
6X 0.075 mm
TOP VIEW
(Seen Through Package)
Metal Pads Far Side
6X 0.350 mm
±0.030
mm
4X 0.575 mm
4X 0.475 mm
2X 0.100 mm
6X 0.400 mm
2X 0.900 mm
Bias
RF2
RF2
N/C
RF1
RF1
2X 0.400 mm
6X 0.300 mm
4X 0.100 mm
6X PCB Top Solder
Mask Opening
4X PCB Top Metal
RF2
RF2
4X PCB Top Metal
6X PCB Top Solder
Mask Opening
Recommended PCB Pad Layout
For 6 Pin Package
(Metal Defined Pads)
2X 0.200 mm
Recommended PCB Pad Layout
For 6 Pin Package
(Solder Mask Defined Pads)
Note:
2X means 2 sites with the specific value
3X means 3 sites with the specific value
4X means 4 sites with the specific value
0.9 mm pad layout is standard for all products. Shorter pad layouts can be considered for smaller products.
Figure 6. QFN Package Dimensions
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4
TCP−3039H
Wafer Level Chip Scale Package (WLCSP) Layout and Dimensional Information
D3
A2
D2
(Copper Pillar
Height)
D1
C1
C2
2X 0.104 mm (Typ)
(Copper Pillar)
C3
B3
A1
B2
N/C Bias
2X 0.069 mm (Typ)
(Copper Pillar)
RF1 RF2
RF1 RF2
RF1 RF2
RF1 RF2
RF Pillars
0.104 mm (Typ)
B2
Top View
(Pillars Down)
Note:
2X means 2 sites with the specific value
3X means 3 sites with the specific value
4X means 4 sites with the specific value
Side View
B4
B1
Bottom View
(Pillars Up)
RF Pillars
0.069 mm (Typ)
Figure 7. WLCSP Package Dimensions
Table 3. PACKAGE DIMENSIONS
(All dimensions are in millimeters)
WLCSP*
8P
10P
12P
14P
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
DIM
A1
A1
A1
A1
A2
B1
B2
B3
B4
C1
C2
C3
D1
D2
D3
Nominal
0.879
1.029
1.179
1.329
0.722
0.460
0.150
0.300
0.131
0.1485
0.425
0.130
0.530
0.081
0.611
Note:
0.9 mm pad layout is standard for all products. Shorter pad
layouts can be considered for smaller products.
Max
Device
1.2, 2.7 pF
3.3, 3.9 pF
4.7, 5.6, 6.8, 8.2 pF
Figure 8. Recommended Pad Layout
*Total number of pillars
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