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PO74G74A_14

Description
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
File Size2MB,7 Pages
ManufacturerPotato Semiconductor Corporation
Websitehttp://www.potatosemi.com/
Download Datasheet View All

PO74G74A_14 Overview

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

PO54G74A, PO74G74A
www.potatosemi.com
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
54, 74 Series Noise Cancellation GHz Logic
FEATURES:
. Patented technology
. Specified From –40°C to 125°C, –55°C to 125°C
. Operating frequency is faster than 600MHz
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 2ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 14pin 150mil wide SOIC package
. Available in 14pin Ceramic Dual Flatpack
. Available in 20pin Leadless Ceramic Chip Carrier
DESCRIPTION:
Potato Semiconductor’s PO74G74A is designed for
world top performance using submicron CMOS
technology to achieve higher than 600MHz TTL
/CMOS output frequency with less than 2ns propaga-
tion delay.
This dual D flip-flop is designed for 1.65-V to 3.6-V
V
CC
operation.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
14
13
12
10
11
9
8
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
1CLK
NC
1PRE
NC
1Q
4
5
6
7
8
3
1CLR
NC
V
CC
2 1 20 19
18
17
16
2CLR
2D
NC
2CLK
NC
2PRE
14
Vcc
2CLR
2D
2CLK
2PRE
2Q
2Q
13
12
11
10
9
8
Pin Description
PRE
L
H
H
H
H
L
CLR
H
L
H
H
H
L
L
INPUTS
CLK
X
X
X
D
X
X
H
L
X
X
OUTPUTS
Q
H
L
L
H
L
Q
0
Q
L
H
L
L
Logic Block Diagram
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
CLR
7
D
PRE
Q
Q
D
PRE
Q
Q
H
Q
0
Potato Semiconductor Corporation
1
1Q
GND
NC
1
2
1D
15
14
9 10 11 12 13
CLR
2Q
2Q
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