PO74G112A
www.potatosemi.com
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
74 Series Noise Cancellation GHz Logic
FEATURES:
. Patented technology
. Specified From –40°C to 85°C, –40°C to 125°C,
and –55°C to 125°C
. Operating frequency up to 750MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 2ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 16pin 150mil wide SOIC package
. Available in 16pin 173mil wide TSSOP package
DESCRIPTION:
Potato Semiconductor’s PO74G112A is designed for
world top performance using submicron CMOS
technology to achieve 750MHz TTL /CMOS output
frequency with less than 2ns propagation delay.
This dual negative-edge-triggered J-K flip-flop is
designed for 1.65-V to 3.6-V V
CC
operation.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
10
9
11
Logic Block Diagram
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
Pin Description
PRE
L
H
H
L
CLR
H
L
L
INPUTS
CLK
X
X
X
J
X
X
L
X
K
X
X
L
X
L
Q
H
H
L
OUTPUTS
Q
L
H
L
H
1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND
J
K
PRE
Q
1
Q
CLR
J
K
PRE
Q
1
Q
CLR
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
H
H
H
H
H
H
H
X
L
Q
0
H
L
Q
0
Q
0
H
Q
0
H
H
H
H
H
H
X
H
Toggle
Potato Semiconductor Corporation
1
01/01/10
PO74G112A
www.potatosemi.com
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
74 Series Noise Cancellation GHz Logic
Maximum Ratings
Description
Storage Temperature
Operation Temperature
Operation Voltage
Input Voltage
Output Voltage
Max
-65 to 150
-55 to 125
-0.5 to +4.6
-0.5 to +5.5
-0.5 to Vcc+0.5
Unit
°C
°C
V
V
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
Output High voltage
Output Low voltage
Input High voltage
Input Low voltage
Input High current
Input Low current
Clamp diode voltage
Test Conditions
Vcc=3V Vin=V
IH
or V
IL
, I
OH
= -12mA
Vcc=3V Vin=V
IH
or V
IL
, I
OH
=12mA
Guaranteed Logic HIGH Level (Input Pin)
Guaranteed Logic LOW Level (Input Pin)
Vcc = 3.6V and Vin = 5.5V
Vcc = 3.6V and Vin = 0V
Vcc = Min. And
I
IN
= -18mA
Min
Typ
Max
Unit
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
V
IK
Notes:
1.
2.
3.
4.
5.
2.4
-
2
-0.5
-
-
-
3
0.3
-
-
-
-
-0.7
-
0.5
5.5
0.8
1
-1
-1.2
V
V
V
V
uA
uA
V
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25
°C
ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
Potato Semiconductor Corporation
2
01/01/10
PO74G112A
www.potatosemi.com
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
74 Series Noise Cancellation GHz Logic
Power Supply Characteristics
Symbol
Description
Quiescent Power Supply Current
Test Conditions (1)
Vcc=Max, Vin=Vcc or GND
Min
Typ
Max
Unit
Icc
Q
Notes:
1.
2.
3.
4.
-
0.1
40
uA
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Capacitance
Parameters (1)
Description
Input Capacitance
Output Capacitance
Test Conditions
Vin = 0V
Vout = 0V
Typ
Unit
Cin
Cout
Notes:
4
6
pF
pF
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
Setup time before CLK
Hold time, data after CLK
Propagation Delay CLK to Q or Q
Propagation Delay CLK to Q or Q
Propagation Delay CLR or PRE to Q or Q
Propagation Delay CLR or PRE to Q or Q
Rise/Fall Time
Input Frequency
CL = 15pF
CL = 15pF
CL = 15pF
CL = 15pF
0.8V – 2.0V
CL=2pF - 15pF
Test Conditions (1)
M ax
t
su
t
h
t
PLH
t
PHL
t
PLH
t
PHL
tr/tf
fmax
Notes:
-
-
Min
Unit
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
MHz
2
2
3
3
0.8
750
-
-
-
-
-
-
1. See test circuits and waveforms.
2.
t
PLH
,
t
PHL
,
t
su, and
t
h are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 500MHz
Potato Semiconductor Corporation
3
01/01/10
PO74G112A
www.potatosemi.com
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
74 Series Noise Cancellation GHz Logic
Test Waveforms
Timing
Input
t
w
V
I
Input
V
M
VOLTAGE WAVEFORMS
PULSE DURATION
V
M
0V
Data Input
t
su
V
M
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
M
t
h
V
M
V
I
0V
V
I
0V
Input
t
PLH
Output
t
PHL
Output
V
M
V
M
t
PHL
V
M
V
M
t
PLH
V
M
V
M
V
I
0V
V
OH
V
OL
V
OH
V
OL
Output
Control
Output
Waveform 1
S1 at V
LOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
V
M
V
M
t
PLZ
V
M
V
OL
+ V
t
PHZ
V
M
V
OH
- V
V
I
0V
V
LOAD
/2
V
OL
V
OH
0V
t
PZH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Test Circuit
Vcc
Pulse
Generator
D.U.T
50Ohm
15pF
to
2pF
Potato Semiconductor Corporation
4
01/01/10
PO74G112A
www.potatosemi.com
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET
74 Series Noise Cancellation GHz Logic
Packaging Mechanical Drawing: 16 pin SOIC
16
.149
.157
3.78
3.99
.2284
.2440
5.80
6.20
1
.386
.393
9.80
10.00
.0075
.0098
0.19
0.25
.016
.050
0.41
1.27
.0155 0.393
.0260 0.660
.053
.068
.0040
.0098
1.35
1.75
0.10
0.25
.050
BSC
1.27
.013
.020
0.330
0.508
X.XX
DENOTES DIMENSIONS
X.XX
IN MILLIMETERS
Packaging Mechanical Drawing: 16 pin TSSOP
X.XX
DENOTES DIMENSIONS
X.XX
IN MILLIMETERS
Potato Semiconductor Corporation
5
01/01/10
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