Delivering Next Generation Technology
Series
FPLR12TR7525*A
6-14Vdc Input, 25A, 0.7525-5.5Vdc Output
The
Series of non-isolated dc-dc converters
deliver
exceptional
electrical
and
thermal
performance in industry-standard footprints for
Point-of-Load converters. Operating from a
6.0Vdc-14Vdc input, these are the converters of
choice for Intermediate Bus Architecture (IBA) and
Distributed Power Architecture applications that
require high efficiency, tight regulation, and high
reliability in elevated temperature environments with
low airflow.
非絶縁型DC/DC½ﾝﾊﾞ½ﾀの
½ﾘ½½½ﾞは業界標準のPOL½ﾝﾊﾞ½ﾀ
と同じ端子配列で極めて優れた電気的特性、及び温度特性を提供しま
す。
入力電圧6V½14Vで動½しますので、この½ﾝﾊﾞ½ﾀは、高効率、高い出
力電圧精度、高温、及び風量の少ない環境での高信頼性が要求される
IBA、又はDPAでの½用に最適です。
FPLR12TR7525*A
Features
•
Delivers up to 25A (137.5W)
25A
(137.5W)まで供給可½
The
FPLR12TR7525*A
converter of the
Series delivers 25A of output current at a tightly
regulated programmable output voltage of 0.7525Vdc
to 5.5Vdc. The thermal performance of the
FPLR12TR7525*A
is best-in-class: Little derating is
needed up to 85℃, under natural convection.
½ ﾘ ½ ½½ ﾞ の FPLR12TR7525*A は 高 い 電 圧 精 度 で 0.7525V ½
5.5Vdcの可変を実現します。FPLR12TR7525*Aの温度特性は½ﾗ½½最高
ﾚﾍﾞﾙです。自然対流、85℃の条件で、わずかなﾃﾞ½ﾚ½ﾃ½ﾝ½ﾞしか必要と
しません。
•
High efficiency, no heatsink required
高効率-放熱器が不要
•
Negative and Positive ON/OFF logic
ON/OFFﾛ½ﾞ½½はﾈ½ﾞﾃ½ﾌﾞとﾎﾟ½ﾞﾃ½ﾌﾞ
•
Industry-standard SIP pin-out
業界標準のSIPピンレイアウト
•
RoHS compliance
RoHS準拠
This leading edge thermal performance results from
electrical, thermal and packaging design that is
optimized for high density circuit card conditions.
Extremely high quality and reliability are achieved
through advanced circuit and thermal design
techniques and FDK’s state of the art in-house
manufacturing processes and systems.
回路設計、放熱設計、及びﾊﾟ½½½½ﾞﾝ½ﾞ設計の結果である、この最先端
の温度特性は、高密度実装回路用に最適化されています。非常に優れ
た品質と信頼性は高度な回路設計、温度設計技術、及びFDKの最先
端の自社½造ﾌﾟﾛ½½½によりもたらされます。
•
Small size and low profile:2.00” x 0.535” x 0.315”
nominal
小型、½背 (50.8 x 13.6 x 8.0mm)
•
Programmable output voltage via external resistor
外部接続の抵抗によりﾌﾟﾛ½ﾞﾗﾑ可½な出力電圧
•
No minimum load required
最小負荷は不要
•
Start up into pre-biased output
出力にﾌﾟﾘﾊﾞ½½½½があっても起動可½
•
Remote ON/OFF
ﾘﾓ½ﾄON/OFF機½
Applications
•
Intermediate Bus Architecture
中間ﾊﾞ½½構成½½½ﾃﾑ
•
Auto-reset output over-current protection
過電流保護機½: 自動復帰
•
Auto-reset output over-temperature protection
内部加熱保護機½
•
High reliability, MTBF = 1 Million Hours
高信頼性: MTBF = 1 Million Hours
•
Telecommunications
ﾃﾚ½ﾑ½½½ﾃﾑ
•
Data/Voice processing
ﾃﾞ½ﾀ処理½½½ﾃﾑ
•
UL60950 recognition in U.S. & Canada, and CB
Scheme certification per IEC/EN60950
UL60950、CB Scheme
•
Distributed Power Architecture
分散型電源½½½ﾃﾑ
•
All materials meet UL94, V-0 flammability rating
全ての部品は UL94 V-0に適合
•
Computing (Servers, Workstations)
½ﾝﾋﾟ½½ﾀ関係(½½ﾊﾞ½、ﾜ½½½½ﾃ½½½ﾝ)
http://www.fdk.co.jp
Page 1 of 26
Ver 2.1 Sep. 26, 2008
Delivering Next Generation Technology
Series
FPLR12TR7525*A
Electrical Specifications
6-14Vdc Input, 25A, 0.7525-5.5Vdc Output
電気的仕様
All specifications apply over specified input voltage, output load, and temperature range, unless otherwise
noted.
注記が無い場合、全ての仕様は指定された入力電圧、負荷、温度範囲で適用されます。
Conditions: Ta=25degC, Airflow=200LFM (1.0m/s), Vin=12Vdc, Vout=0.7525-5.5Vdc, unless otherwise specified.
PARAMETER
ABSOLUTE MAXIMUM RATINGS
1
Input Voltage
Operating Temperature
Storage Temperature
Output Voltage
FEATURE CHARACTERISTICS
Switching Frequency
Output Voltage Programming Range
R
emote
Sense Compensation
Turn-On Delay Time
with Vin (module enabled, then Vin applied)
with Enable (Vin applied, then enabled)
Rise Time (Full resistive load)
ON/OFF Control (Negative)
Module Off
Module On
ON/OFF Control (Positive)
Module Off
Module On
Continuous
NOTES
MIN
TYP
MAX
UNITS
-0.3
-40
-55
0.7525
15
85
125
5.5
Vdc
°C
°C
Vdc
Ambient temperature
320
By external resistor. See trim table-1
0.7525
5.5
0.5
Full resistive load
From Vin=Vin(min) to 0.1*Vout(nom)
From enable to 0.1*Vout(nom)
From 0.1*Vout(nom) to 0.9*Vout(nom)
5.0
5.0
5.0
kHz
Vdc
Vdc
ms
ms
ms
2.4
-5
Vin
0.8
Vdc
Vdc
-5
Vin-1.0
Vin-2.7
Vin
Vdc
Vdc
1
Absolute Maximum Ratings
絶対最大定格
Stresses in excess of the absolute maximum ratings may lead to degradation in performance and reliability of
the converter and may result in permanent damage.
絶対最大定格を超えた½½ﾄﾚ½½は、性½の½下、長期信頼性の½下、及びﾓ½ﾞ½½ﾙの破損を引き起こすことがあります。
http://www.fdk.co.jp
Page 2 of 26
Ver 2.1 Sep. 26, 2008
Delivering Next Generation Technology
Series
FPLR12TR7525*A
6-14Vdc Input, 25A, 0.7525-5.5Vdc Output
Electrical Specifications (Continued)
PARAMETER
INPUT CHARACTERISTICS
Operating Input Voltage Range
電気的仕様 (続き)
Conditions: Ta=25degC, Airflow=200LFM (1.0m/s), Vin=12Vdc, Vout=0.7525-5.5Vdc, unless otherwise specified.
NOTES
MIN
TYP
MAX
UNITS
Vout≦3.8Vdc (3.3Vdc+15%)
Vout＞3.8Vdc (3.3Vdc+15%)
6
8
12
12
14
14
Vdc
Vdc
Input Under Voltage Lockout
Turn-on Threshold
Turn-off Threshold
Maximum Input Current
25Adc out at 6.0Vdc in
Vout=5.0Vdc (25Adc at 8.0Vdc in)
Vout=3.3Vdc
Vout=2.5Vdc
Vout=2.0Vdc
Vout=1.8Vdc
Vout=1.5Vdc
Vout=1.2Vdc
Vout=1.0Vdc
Input Stand-by Current (module disabled)
Input No Load Current
Vout=5.0Vdc
Vout=3.3Vdc
Vout=2.5Vdc
Vout=2.0Vdc
Vout=1.8Vdc
Vout=1.5Vdc
Vout=1.2Vdc
Vout=1.0Vdc
Input Reflected-Ripple Current
See Fig. F for setup (BW=20MHz)
Vout=5.0Vdc
Vout=3.3Vdc
Vout=2.5Vdc
Vout=2.0Vdc
Vout=1.8Vdc
Vout=1.5Vdc
Vout=1.2Vdc
Vout=1.0Vdc
50
40
35
35
30
25
20
20
mAp-p
mAp-p
mAp-p
mAp-p
mAp-p
mAp-p
mAp-p
mAp-p
2.4
90
69
56
48
44
40
36
33
16.5
14.9
11.6
9.3
8.5
7.2
6.0
5.2
Adc
Adc
Adc
Adc
Adc
Adc
Adc
Adc
mA
mA
mA
mA
mA
mA
mA
mA
mA
5.4
4.3
Vdc
Vdc
http://www.fdk.co.jp
Page 3 of 26
Ver 2.1 Sep. 26, 2008
Delivering Next Generation Technology
Series
FPLR12TR7525*A
6-14Vdc Input, 25A, 0.7525-5.5Vdc Output
Electrical Specifications (Continued)
PARAMETER
OUTPUT CHARACTERISTICS
Output Voltage Set Point (no load)
Output Regulation
Over Line
Over Load
Output Voltage Range
(Over all operating input voltage, resistive load
and temperature conditions until end of life)
Output Ripple and Noise BW=20MHz
Peak to Peak
Peak to Peak
External Load Capacitance
Min ESR > 1mΩ
Min ESR > 10mΩ
Output Current Range
Output Current Limit Inception (Iout)
Output Short-Circuit Current
DYNAMIC RESPONSE
Iout step from 12.5A to 25A with di/dt= 5A/µS
Setting time (Vout < 10% peak deviation)
Iout step from 25A to 12.5A with di/dt= 5A/µS
Setting time (Vout < 10% peak deviation)
EFFICIENCY
電気的仕様 (続き)
NOTES
MIN
TYP
MAX
UNITS
Conditions: Ta=25degC, Airflow=200LFM (1.05m/s), Vin=12Vdc, Vout=0.7525-5.5Vdc, unless otherwise specified.
-1.5
Vout
+1.5
%Vout
Full resistive load
From no load to full load
-2.5
Over line, load and temperature (Fig. E)
Vout=1.0Vdc
Vout=5.0Vdc
Plus full load (resistive)
+/- 0.1
+/- 0.4
+2.5
%Vout
%Vout
%Vout
15
25
80
80
mVp-p
mVp-p
1,000
5,000
0
Vout=3.3Vdc
Short=10mΩ, Vout=3.3Vdc set
35
8.3
25
µF
µF
A
A
Arms
Co=47µF x 2 ceramic + 1µF ceramic
160
40
mV
µS
mV
µS
Co=47µF x 2 ceramic + 1µF ceramic
160
40
Full load (25A)
Vout=5.0Vdc
Vout=3.3Vdc
Vout=2.5Vdc
Vout=2.0Vdc
Vout=1.8Vdc
Vout=1.5Vdc
Vout=1.2Vdc
Vout=1.0Vdc
95.0
93.0
91.5
89.5
88.5
86.5
84.0
81.5
%
%
%
%
%
%
%
%
http://www.fdk.co.jp
Page 4 of 26
Ver 2.1 Sep. 26, 2008
Delivering Next Generation Technology
Series
FPLR12TR7525*A
Operation
Input and Output Impedance
The
FPLR12TR7525*A
converter should be
connected to a DC power source using a low
impedance input line. In order to counteract the
possible effect of input line inductance on the stability
of the converter, the use of decoupling capacitors
placed in close proximity to the converter input pins is
recommended. This will ensure stability of the
converter and reduce input ripple voltage. Although
low ESR Tantalum or other capacitors should
typically be adequate, very low ESR capacitors
(ceramic, over 200µF) are recommended to minimize
input ripple voltage. The converter itself has on-board
internal input capacitance of 10µF with very low ESR
(ceramic).
FPLR12TR7525*Aと入力電源間は½½ﾝﾋﾟ½ﾀﾞﾝ½½で接続してください。½ﾝ
ﾊﾞ½ﾀの安定性に½響のある入力½ﾝﾀﾞ½ﾀﾝ½½を抑えるため、½ﾝﾊﾞ½ﾀの入
力ﾋﾟﾝの近傍にﾃﾞ½½ﾌﾟﾘﾝ½ﾞ½ﾝﾃﾞﾝ½を付加することをお勧めします。これ
により½ﾝﾊﾞ½ﾀの安定動½を確実にし、入力ﾘ½ﾌﾟﾙ電圧を抑制します。½
ESRﾀﾝﾀﾙ、又はその他の½ﾝﾃﾞﾝ½も一般的には問題ありませんが、入
力ﾘ½ﾌﾟﾙを最小にするためには、非常に½ESR½ﾝﾃﾞﾝ½(½ﾗﾐ½½で200μF
以上)を推奨します。½ﾝﾊﾞ½ﾀ自身は入力回路に極½ESRの10μF½ﾗﾐ½½
入力½ﾝﾃﾞﾝ½を搭載しています。
6-14Vdc Input, 25A, 0.7525-5.5Vdc Output
ON/OFF (Pin 10)
The ON/OFF pin (pin 10) can be used to turn the
converter on or off remotely using a signal that is
referenced to GND (pin 5 & 6), as shown in Fig. A.
Two remote control options are available,
corresponding to negative and positive logic. In the
negative logic option, to turn the converter on Pin 10
should be at logic low or left open, and to turn the
converter off Pin 10 should be at logic high or
connected to Vin. In the positive logic option, to turn
the converter on Pin 10 should be at logic high,
connected to Vin or left open, and to turn the
converter off Pin 10 should be at logic low.
ON/OFF端子(10番ﾋﾟﾝ)は図Aのように、½ﾞﾗﾝﾄﾞ(5番ﾋﾟﾝ、6番ﾋﾟﾝ)を基準と
したﾘﾓ½ﾄ信号により½ﾝﾊﾞ½ﾀをON/OFFするのに½われます。 ﾈ½ﾞﾃ½ﾌﾞ
とﾎﾟ½ﾞﾃ½ﾌﾞﾛ½ﾞ½½に対応するため、2種類のﾘﾓ½ﾄ½ﾝﾄﾛ½ﾙを選択可½で
す。
ﾈ½ﾞﾃ½ﾌﾞ½ﾌﾟ½½ﾝの場合、½ﾝﾊﾞ½ﾀをONするには10番ﾋﾟﾝをLowﾚﾍﾞﾙ、又
は未接続とし、½ﾝﾊﾞ½ﾀをOFFするには10番ﾋﾟﾝをHighﾚﾍﾞﾙ、又はVinと接
続とします。ﾎﾟ½ﾞﾃ½ﾌﾞ½ﾌﾟ½½ﾝの場合、½ﾝﾊﾞ½ﾀをONするには10番ﾋﾟﾝを
Highﾚﾍﾞﾙ、Vinに接続、又は未接続とし、½ﾝﾊﾞ½ﾀをOFFするには10番ﾋﾟﾝ
をLowﾚﾍﾞﾙにします。
The
FPLR12TR7525*A
is capable of stable operation
with no external capacitance on the output. To
minimize output ripple voltage, the use of very low
ESR ceramic capacitors is recommended. These
capacitors should be placed in close proximity to the
load to improve transient performance and to
decrease output voltage ripple.
FPLR12TR7525*Aは出力に外付け½ﾝﾃﾞﾝ½が無い状態でも安定して動
½します。出力ﾘ½ﾌﾟﾙを最小にするため、極½ESRの½ﾗﾐ½½½ﾝﾃﾞﾝ½の接
続を推奨します。過渡時の特性向上と出力ﾘ½ﾌﾟﾙ½減のために負荷の
近傍に極½ESR½ﾗﾐ½½½ﾝﾃﾞﾝ½を実装することをお勧めします。
For a positive logic option, the ON/OFF pin (pin10) is
internally pulled-up to Vin. An open collector (open
-drain) transistor can be used to drive Pin 10.
The device driving Pin 10 must be capable of:
(a) Sinking up to 0.3mA at low logic level
ﾎﾟ½ﾞﾃ½ﾌﾞ½ﾌﾟ½½ﾝの場合、ON/OFFﾋﾟﾝはﾓ½ﾞ½½ﾙ内部でVinにﾌﾟﾙ½½ﾌﾟさ
れています。½½ﾌﾟﾝ½ﾚ½ﾀ（½½ﾌﾟﾝﾄﾞﾚ½ﾝ）のﾄﾗﾝ½ﾞ½½ﾀがON/OFFﾋﾟﾝの操
½に½用可½です。
ON/OFFﾋﾟﾝを操½するﾃﾞﾊﾞ½½½には下記½力が必要です。
(a) Lowﾚﾍﾞﾙで0.3mA程度の½ﾝ½½力
Note that the converter has a SENSE pin to
counteract voltage drops between the output pins
and the load. However, the impedance of the line
from the converter output to the load should thus be
kept as low as possible to maintain good load
regulation.
この½ﾝﾊﾞ½ﾀは出力端子と負荷間の電圧ﾄﾞﾛ½ﾌﾟを補正する½ﾝ½½端子を
持っています。しかし、精度の高い負荷特性を保持するために、½ﾝﾊﾞ½ﾀ
の出力から負荷までのﾗ½ﾝ½ﾝﾋﾟ½ﾀﾞﾝ½½は可½な限り½くしてください。
For a negative logic option, the ON/OFF pin (pin10) is
internally pulled-down. A TTL or CMOS logic gate, or
an open collector (open-drain) transistor can be used
to drive Pin 10. When using an open collector (open
-drain) transistor, a pull-up resistor, R*=75kΩ, should
be connected to Vin (See Fig.A).
The device driving Pin 10 must be capable of:
(b) Sinking up to 0.2mA at low logic level (≦0.8V)
(c) Sourcing up to 0.25mA at high logic level (2.3–5V)
(d) Sourcing up to 0.75mA when connected to Vin
ﾈ½ﾞﾃ½ﾌﾞ½ﾌﾟ½½ﾝの場合、ON/OFFﾋﾟﾝはﾓ½ﾞ½½ﾙ内部でﾌﾟﾙﾀﾞ½ﾝされてい
ます。TTL、 CMOSﾛ½ﾞ½½、又は½½ﾌﾟﾝ½ﾚ½ﾀ（½½ﾌﾟﾝﾄﾞﾚ½ﾝ）のﾄﾗﾝ½ﾞ½½ﾀも
ON/OFFﾋﾟﾝの操½に½用可½です。½½ﾌﾟﾝ½ﾚ½ﾀ（½½ﾌﾟﾝﾄﾞﾚ½ﾝ）のﾄﾗﾝ½ﾞ
½½ﾀを½用する時は75kΩのﾌﾟﾙ½½ﾌﾟ抵抗をVinに接続してください。
(図A参照)
ON/OFFﾋﾟﾝを操½するﾃﾞﾊﾞ½½½には下記½力が必要です。
(b) 0.8V以下のLowﾚﾍﾞﾙで0.2mAまでの½ﾝ½½力
(c) 2.3V-5VのHighﾛ½ﾞ½½ﾚﾍﾞﾙで0.25mAまでの供給½力
(d) Vin接続時には0.75mAまでの供給½力
Vin
R*
Vin
ON/OFF
SENSE
Vout
GND
CONTROL
INPUT
TRIM
Rload
R* is for negative logic option only
Fig. A: Circuit configuration for remote ON/OFF
http://www.fdk.co.jp
Page 5 of 26
Ver 2.1 Sep. 26, 2008
京公网安备 11010802033920号
EEWORLD
